DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 – 4 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2009/0107701).
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(Claim 1) Park et al. teach a semiconductor package comprising:
a package substrate (10) including upper pads (12) disposed at an upper portion of the package substrate;
a solder resist layer (16) disposed on the package substrate, the solder resist layer having a plurality of openings (openings for #32, openings for #18) exposing the upper pads;
a first adhesive layer (18 up to the height coplanar with 16, 18 up to the height coplanar with 12) disposed in at least a portion of an opening of the plurality of openings;
a semiconductor chip (30) disposed on the first adhesive layer;
a second adhesive layer (18 from height coplanar with 12 to the underside of 30) disposed between the first adhesive layer and the semiconductor chip; and
a conductive member (32) electrically connecting at least one of the upper pads (12) and the semiconductor chip (30) to each other.
(Claim 3) Park et al. teach wherein an upper surface of the first adhesive layer (18 up to the height coplanar with 16) is at a level that is the same as that of an upper surface of the solder resist layer (16).
(Claim 4) Park et al. teach wherein an upper surface of the first adhesive layer (18 up to the height coplanar with 12) is at a level that is lower than that of an upper surface of the solder resist layer (16).
(Claim 12) Park et al. teach wherein the first adhesive layer includes an underfill material (paragraph 47).
Claims 13, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2005/0093179).
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(Claim 13) Andoh teaches a semiconductor package comprising:
a package substrate (40) including upper pads (32a) and insulating layers (30-1) disposed at an upper portion of the package substrate;
a solder resist layer (34a, 34C) disposed on a first surface of the package substrate, the solder resist layer having a first opening (opening of #44) exposing an upper surface of at least one upper pad (32a) and a second opening (opening between P” and Q”) exposing at least a portion of an upper surface of the insulating layer (30-1),
the second opening having a width wider than that of the first opening;
a first adhesive layer (paragraph 37, #26 below/up to a height coplanar with the top of 34C) disposed in the second opening, the first adhesive layer (26 up to the height coplanar with the top of 34C) covering the upper surface of the insulating layer (30-1) exposed in the second opening,
the first adhesive layer (26 up to the height coplanar with the top of 34C) in contact with the solder resist layer (34c);
a second adhesive layer (the remainder of #26 from first adhesive layer) disposed on the first adhesive layer; and
a semiconductor chip (24) disposed on the second adhesive layer, the semiconductor chip (24) electrically connected to a redistribution layer (40-1 – 40-3) through the at least one upper pad (32a) exposed by the first opening.
(Claim 14) Andoh teaches wherein an upper surface of the first adhesive layer is at a level (height coplanar with the top of 34C) that is the same as that of an upper surface of the solder resist layer.
(Claim 16) Andoh teaches wherein an upper surface of the first adhesive layer is at a level (height below the top of 34C) that is lower than that of an upper surface of the solder resist layer.
Allowable Subject Matter
Claims 2, 5 – 11 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17 – 20 are allowable, because prior art does not render obvious:
(Claim 17) a second adhesive layer disposed between the first adhesive layer and the semiconductor chip, the second adhesive layer having a second coefficient of thermal expansion, lower than the first coefficient of thermal expansion.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
July 15, 2026
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