DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, reads on claims 1-4 and 6 in the reply filed on 11/26/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Yamaji (US 2020/0044652).
Regarding claim 1, Yamaji discloses a switching control circuit [fig. 3] configured to control switching of a first switching device [QH] on a power supply side [Vdc] and a second switching device [QL] on a ground side [COM], the first and second switching devices being configured to drive a load [external connect to OUT], the first switching device having an electrode [emitter QH] on a low-potential side [VS] thereof, the switching control circuit comprising: a first level shifter circuit [includes Rsf1, Tr1, HVN1, Rls1, par. 0006-0007] including a first resistor [Rsf1] and a first transistor [HVN1]; a driver circuit [DRV] configured to drive the first switching device, in response to an output from the first level shifter circuit [output to INV1]; a first switch [Tr1] connected in parallel with the first resistor; and an ON-OFF control circuit [COMP] configured to turn on the first switch [par. 0050], in response to a voltage at the electrode becoming negative [par. 0008 and 0048-0050].
Regarding claim 2, Yamaji discloses [fig. 3] further comprising : a second level shifter circuit [includes Rsf2, Tr2, HVN2, Rls2, par. 0006-0007] including a second resistor [Rls2] and a second transistor [HVN2], wherein the first level shifter circuit is configured to output a set signal [SET] to switch the first switching device from off to on, the second level shifter circuit is configured to output a reset signal [RST] to switch the first switching device from on to off, and the driver circuit drives the first switching device in response to the set signal and the reset signal.
Regarding claim 3, Yamaji discloses [fig. 3] further comprising: a second switch connected in parallel [Tr2] with the second resistor, wherein the ON-OFF control circuit is configured to turn on the second switch, in response to the voltage at the electrode becoming negative [par. 0008 and 0048-0050].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaji.
Regarding 4, Yamaji discloses all the features with respect to claim 3 as outlined above. Yamaji further discloses wherein each of the first transistor and the second transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor [par. 0031], and each of the first switch and the second switch is n-channel metal-oxide-semiconductor (NMOS) transistor [N-channel MOSFET]. Yamaji does not explicitly disclose first switch and the second switch is a p-channel metal-oxide-semiconductor (PMOS). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the transistors of Yamaji with an P-type MOSFETs because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent transistor device.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6. Yamaji discloses [fig. 3], wherein the ON-OFF control circuit includes: a diode element [D4/D5] configured to pass a current when the voltage at the electrode is negative, but is silent with respect to the above structure in combination with a signal output circuit configured to output a signal to turn on the first switch and to keep the first switch on for a predetermined time period, based on the current flowing through the diode element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842