DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 4 and 10 are objected to because of the following informalities: in claim 1, line 4, include a semicolon at the end of the line; in claim 4, line 2, replace the word “connecting” with --connection-- for continuity with claim language; and in claim 10, replace to word “including” with --includes-- for grammatical clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the via structure" in line 14 and the limitation “the first upper line pattern” in line 18. There is insufficient antecedent basis for these limitations in the claim.
Claim 2 recites the limitation "the upper via pattern" in line 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of this Office Action, it is assumed that the claim is intended to speak to “the first upper via pattern,” as the limitation is introduced in the independent claim 1 from which claim 2 depends.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Patent Application Publication 2022/0230912) in view of Yoo et al (US Patent Application Publication 2021/0028098).
Regarding claim 1, Kim et al disclose an integrated circuit package, comprising:
a lower redistribution structure 300;
a connection structure 400 on the lower redistribution structure including a cavity TH therein;
a semiconductor chip 100 within the cavity, and on the lower redistribution structure;
a molding layer ENC1 that at least partially fills the cavity, and at least partially covers the connection structure and an upper part of the semiconductor chip, the molding layer including an upper through hole VH1 therein, which extends inward from an upper surface thereof [see Fig. 1; see also paragraph 0041];
an upper structure including: an upper insulating layer 600 on the molding layer, a first protrusion ENC2 located inside the upper through hole, and an upper pattern that includes a first upper via pattern VS located inside the first protrusion [see Fig. 2; see also paragraph 0039];
wherein the upper through hole of the molding layer is above the via structure of the connection structure [see Fig. 1];
wherein the first upper via pattern is electrically connected to the via structure of the connection structure [see Figs. 1-3 and 12]; and
wherein a portion of the first upper line pattern of the upper redistribution structure is buried in the upper insulating layer [see Figs. 1-3 and 12].
Kim et al do not disclose specifically wherein the upper structure comprises an upper redistribution structure, nor consequently wherein the upper pattern is an upper redistribution pattern. One such as Yoo et al disclose a lower redistribution structure 101; a connection structure on the lower redistribution structure including a cavity therein; a semiconductor chip 210 within the cavity, and on the lower redistribution structure; a molding layer 251a that at least partially covers the connection structure and an upper part of the semiconductor chip, the molding layer including an upper through hole therein, which extends inward from an upper surface thereof [see Fig. 3]; and an upper redistribution structure 401 including: an upper insulating layer 410 on the molding layer, and an upper redistribution pattern 420 that includes a first upper via pattern. It would have been obvious to one of ordinary skill in the art at the time of invention to include the upper redistribution structure of Yoo et al as the upper structure of Kim et al in order to redistribute the electrical connection provided by the vertical via structure of Kim et al laterally to a desired location at the upper surface of the semiconductor package, thereby providing greater flexibility in the positioning and routing of upper electrical connections.
Regarding claim 2, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein the first upper via pattern [see the rejection under the second paragraph of 35 U.S.C. §112 above] of the upper redistribution structure is at least partially surrounded by the first protrusion, and is spaced apart from the molding layer in a horizontal direction [see Fig. 2].
Regarding claim 4, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein the horizontal width of the first protrusion of the upper insulating layer narrows in a direction towards the connection structure; and wherein the horizontal width of the first upper via pattern of the upper redistribution pattern narrows in a direction toward the connection structure [see Fig. 2].
Regarding claim 5, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein a slope of a side of the first protrusion of the upper insulating layer is different from a slope of the first upper via pattern of the upper redistribution pattern [see Fig. 2].
Regarding claim 6, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein a constituent material of the molding layer ENC1 is different from a constituent material of the upper insulating layer ENC2 of the upper redistribution pattern [see paragraphs 0040 and 0041].
Regarding claim 8, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore to the upper redistribution structure, Yoo et al disclose wherein the upper redistribution structure includes a first upper line pattern 420 and a second upper line pattern 430 buried within the upper insulating layer 410; and wherein a horizontal level of the first upper line pattern is different from a horizontal level of the second upper line pattern [see Fig. 8P].
Regarding claim 9, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore to the upper redistribution structure, Yoo et al disclose wherein the upper redistribution structure includes a first upper redistribution structure 420 located on the molding layer and a second upper redistribution structure 430 located on the first upper redistribution structure;
wherein the first upper redistribution structure includes a first upper insulating layer 411 including the first protrusion, as disclosed by Kim et al, and a first upper redistribution pattern including the first upper via 423 and the first upper line pattern 421; and
wherein the second upper redistribution structure includes a second upper insulating layer 413 and a second redistribution pattern, which is electrically connected to the first upper redistribution pattern [see Fig. 8P].
Regarding claim 11, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein the semiconductor chip includes a semiconductor substrate including an active surface 100b and an inactive surface 100t facing the active surface, and a wiring structure 110 located on the active surface [see Fig. 1; see also paragraph 0027];
wherein the active surface of the semiconductor chip faces the lower redistribution structure; and
wherein the wiring structure is electrically connected to the lower redistribution structure [see Fig. 1].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Patent Application Publication 2022/0230912) in view of Yoo et al (US Patent Application Publication 2021/0028098) as applied to claim 1 above, and further in view of Kim et al (US Patent Application Publication 2019/0206813), henceforth Kim ‘813.
Regarding claim 7, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Furthermore, Kim et al disclose wherein the molding layer includes a resin; and wherein the upper insulating layer of the upper redistribution structure includes a photosensitive resin [see paragraph 0041]. However, Kim et al do not disclose specifically wherein the resin from which the molding layer is formed is thermosetting in nature. One such as Kim ‘813 teach semiconductor package encapsulants comprising an insulating material including a thermosetting resin, such as an epoxy resin, and further identifies ABF, FR-4, BT or other materials [see paragraph 0082]. It would have been obvious to one of ordinary skill in the art at the time of invention to use the thermosetting resin materials of Kim ‘813 in the package taught by Kim et al, as modified by Yoo et al, because thermosetting resin is a known material in the art for the purpose and would predictably provide the insulating and encapsulating function required by Kim et al. Furthermore, it has been held that simple substitution of one known material for another to obtain predictable results is obvious. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). See MPEP 2143.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Patent Application Publication 2022/0230912) in view of Yoo et al (US Patent Application Publication 2021/0028098) as applied to claim 8 above, and further in view of Pak et al (US Patent Application Publication 2022/0068870).
Regarding claim 10, the prior art of Kim et al and Yoo et al disclose the package of claim 1. Neither Kim et al nor Yoo et al disclose further comprising an upper passivation layer on the upper redistribution structure, wherein the upper passivation layer includes an opening therein that exposes a portion of a second upper line pattern of the second upper redistribution pattern. One such as Pak et al disclose a package having an outermost redistribution structure formed over a semiconductor chip 100, which is analogous to the upper redistribution structure of Yoo et al, furthermore comprising an upper passivation layer 310 on the upper redistribution structure, wherein the upper passivation layer includes an opening therein that exposes a portion of a second upper line pattern of the second upper redistribution pattern [see Fig. 8]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the upper passivation layer of Pak et al in the package of Kim et al, as modified by Yoo et al, in order to protect the upper redistribution structure while leaving a portion of the second upper redistribution pattern available for external electrical connection.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claim 3, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein a horizontal width of the upper insulating layer is in a range from 50 µm to 60 µm, and a horizontal width of the first upper via pattern of the upper redistribution pattern is in a range from 10 µm to 20 µm.
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance: regarding independent claims 12 and 18, and claims 13-17, 19 and 20 which depend therefrom, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, a third upper redistribution structure including a third upper redistribution pattern extending inside the upper through hole and on the molding layer and electrically connected to the via structure, and a third upper insulating layer covering the third upper redistribution pattern, wherein a first upper redistribution structure is formed on the third upper redistribution structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899
