DETAILED ACTION
This action is in response to the 07/17/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1 – 3, 7 – 8, 10 – 15, 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2010/0295521; (hereinafter Odaohhara), cited by Applicant(s) in view of US Pub. No. 2016/0294284; (hereinafter Lerdworatawee), cited by Applicant(s).
Regarding claim 1, Odaohhara [e.g. Fig. 7; paragraph 053 recites “The method of changing the inductance value of the inductor illustrated in FIGS. 6 and 7 can be applied to the FET connection topologies illustrated in FIGS. 4C and 4D. The inductors 355 and 357 and the FET 353 constitute a variable inductor” and paragraph 013 recites “FIGS. 4A to 4D are circuit diagrams illustrating the connection topologies of FETs within the DC/DC converter from FIG. 2”] discloses a voltage converter [e.g. 300] comprising: a variable inductor device [e.g. 353, 355, 357; paragraph 052 recites “FIG. 7 is a block diagram illustrating another example of a DC/DC converter, in which the inductance value of an inductor is variable”] disposed between an input line [e.g. 101] and an output line [e.g. 117]; a switching device [e.g. 103, 105, 107, 109] disposed between the input line and the variable inductor device; a capacitor [e.g. 115] is disposed between the output line and a ground line [e.g. at lower terminal of 115]; and a control circuit [e.g. 250] configured to switch an inductance value of the variable inductor device [e.g. paragraph 053 below] and to switch a control mode of the switching device according to a load current in the output line [e.g. paragraph 028 recites “The operational amplifier 159 and the sense resistor 113 constitute an output current measurement circuit”. Paragraph 030 recites “The driver control circuit 169 determines whether a present load state is a heavy load state or a light load state based on the output of the operational amplifier 159”], wherein the control circuit is further configured to set the inductance value of the variable inductor device to a first value when the load current is less than a threshold value and to set the inductance value of the variable inductor device to a second value that is smaller than the first value when the load current is higher than the threshold value [e.g. paragraph 053 recites “The driver control circuit 351 …turns on the FET 353 so that only the inductor 357 contributes to the reduction of the ripple voltage at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the heavy-load FETs 103 and 105, respectively, based on the output of the operational amplifier 159. The driver control circuit 351 … turns off the FET 353 at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the light-load FETs 107 and 109, respectively”. In summary according to paragraph 052 – 053: the operating states (heavy and low) are determined according to the output current measurement circuit (113 and 159). During “heavy load” FETs 103 and 105 are operated and the FET 353 is ON (inductance is small since only the inductance of inductor 357 is used). During “light load” FETs 107 and 109 are operated and the FET 353 is OFF (inductance is large since the inductance of both inductors are added). Examiner note: There’s a necessary threshold for changing the light and heavy load states, paragraph 030 above].
Odaohhara fails to disclose wherein the variable inductor device includes: a plurality of inductors, and a switching unit that is configured to be opened and closed according to a signal from the control circuit, the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection.
Lerdworatawee [e.g. Fig. 4B] teaches wherein the variable inductor device [e.g. 491] includes: a plurality of inductors [e.g. 416, 417], and a switching unit [e.g. 430, 431, 432] that is configured to be opened and closed according to a signal [e.g. NDRV, NDRVB] from the control circuit [e.g. 410, 411, 415, 416], the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection [e.g. Fig. 5B] and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection [e.g. Fig. 5A; paragraph 032 recites “Reconfigurable inductance 491 may be configured as shown in FIGS. 5A and 5B. In FIG. 5A, NDRV is high and switches 510 and 512 are closed, and NDRVB (NDRV bar, or the inverse of NDRV) is low and switch 511 is open. Accordingly, in this configuration, inductors 501 and 502 are in parallel. In FIG. 5B, NDRVB is high and switch 511 is closed, and NDRV is low and switches 510 and 512 are open. Accordingly, in this configuration, inductors 501 and 502 are in series”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Odaohhara by wherein the variable inductor device includes: a plurality of inductors, and a switching unit that is configured to be opened and closed according to a signal from the control circuit, the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection as taught by Lerdworatawee in order of being able to reduce noise and improve efficiency performance over a wide bandwidth range, paragraph 03.
Regarding claim 2, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is further configured to switch the control mode for the switching device when the inductance value of the variable inductor device is changed [e.g. Paragraph 053 recites “The driver control circuit 351 …turns on the FET 353 so that only the inductor 357 contributes to the reduction of the ripple voltage at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the heavy-load FETs 103 and 105, respectively, based on the output of the operational amplifier 159. The driver control circuit 351 … turns off the FET 353 at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the light-load FETs 107 and 109, respectively”].
Regarding claim 3, Odaohhara [e.g. Fig. 7] discloses wherein the variable inductor device includes: a plurality of inductors [e.g. 355, 357]; and a switching unit [e.g. 353] that is configured to be opened and closed according to a signal from the control circuit [e.g. output of 351] and couples at least one of the plurality of inductors between the switching device and the output line [e.g. when conducting couples 357 to 103, 105 and output line 117; paragraph 053 above with respect to claims 1 – 2].
Regarding claim 7, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is configured to set the control mode for the switching device to a pulse frequency modulation (PFM) control mode when the load current is less than the threshold value and set the control mode to a pulse width modulation (PWM) control mode when the load current is more than the threshold value [e.g. paragraphs 054 – 0 55 recite “A well-known operation mode called an intermittent mode is employed in order to reduce the light-load loss of a PWM switching regulator. The intermittent mode is also referred to as a skip mode, a burst mode, or a sleep mode, for example. The intermittent mode is usually used together with a PWM mode so that the PWM mode is used in the heavy load state, and the intermittent mode is used in the light load state. In the intermittent mode, the On period of the high-side FET is maintained to be constant while ignoring several control pulses during the PWM mode, and the Off period of the high-side FET is controlled so that an output voltage falls within the range of an upper limit and a lower limit. In a switching regulator employing the intermittent mode, it is possible to reduce the switching loss by decreasing the substantial switching frequency to be lower than that in the PWM mode. In this case, the ideas of the present invention regarding the switching of FETs illustrated in FIGS. 2 and 4 and the switching of inductors illustrated in FIGS. 6 and 7 can be applied to the intermittent mode. Although the PWM mode DC/DC converter has been described by way of an example, the present invention can be applied to a PFM mode DC/DC converter. Examiner note: There’s a necessary threshold for changing the light and heavy load states, paragraph 030].
Regarding claim 8, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is configured to: perform a switching of the control mode [e.g. heavy load mode / light load mode] for the switching device according to the load current [e.g. Paragraph 030 recites “The driver control circuit 169 determines whether a present load state is a heavy load state or a light load state based on the output of the operational amplifier 159”]; after the switching of the control mode for the switching device [e.g. after it is determined that the state is light load after heavy load], determine a specific inductance value that increases an efficiency of the voltage converter [e.g. by switching (353) ON (heavy load) and OFF (light load), the efficiency is improved by minimizing ripples according to the inductance value by by-passing the inductance 355 when during heavy load and connected in series both inductors 355,357 during light load”]; and switch the inductance value of the variable inductor device to the specific inductance value [e.g. paragraph 053 recites “The driver control circuit 351 …turns on the FET 353 so that only the inductor 357 contributes to the reduction of the ripple voltage at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the heavy-load FETs 103 and 105, respectively, based on the output of the operational amplifier 159. The driver control circuit 351 …turns off the FET 353 at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the light-load FETs 107 and 109, respectively. By doing so, when the switching frequency is decreased, the total inductance value of the inductors 355 and 357 can be contributed to the reduction of the ripple voltage”].
Regarding claim 10, Odaohhara [e.g. Fig. 7; paragraph 053 recites “The method of changing the inductance value of the inductor illustrated in FIGS. 6 and 7 can be applied to the FET connection topologies illustrated in FIGS. 4C and 4D. The inductors 355 and 357 and the FET 353 constitute a variable inductor” and paragraph 013 recites “FIGS. 4A to 4D are circuit diagrams illustrating the connection topologies of FETs within the DC/DC converter from FIG. 2”] discloses a voltage converter comprising: a switching device [e.g. 103, 105, 107, 109], a variable inductor device [e.g. 353, 355, 357; paragraph 052 recites “FIG. 7 is a block diagram illustrating another example of a DC/DC converter, in which the inductance value of an inductor is variable”] and a capacitor [e.g. 115] that are coupled between an input line [e.g. 101] and an output line [e.g. 117] of the voltage converter to convert an input voltage on the input line to an output voltage on the output line; and a control circuit [e.g. 250] configured to provide one or more first control signals to the switching device [e.g. output signals of 151, 153], and one or more second control signals to the variable inductor device [e.g. output of 351 to gate terminal of FET 353] according to a load current in the output line [e.g. current sensed by 113, 159; [e.g. paragraph 028 recites “The operational amplifier 159 and the sense resistor 113 constitute an output current measurement circuit”. Paragraph 053 recites “Paragraph 053 recites “The driver control circuit 351 …turns on the FET 353 so that only the inductor 357 contributes to the reduction of the ripple voltage at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the heavy-load FETs 103 and 105, respectively, based on the output of the operational amplifier 159. The driver control circuit 351 … turns off the FET 353 at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the light-load FETs 107 and 109, respectively”].
Odaohhara fails to disclose wherein the variable inductor device includes: a plurality of inductors, and a switching unit that is configured to be opened and closed according to the one or more second control signals, the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection.
Lerdworatawee [e.g. Fig. 4B] teaches wherein the variable inductor device [e.g. 491] includes: a plurality of inductors [e.g. 416, 417], and a switching unit [e.g. 430, 431, 432] that is configured to be opened and closed according to the one or more second control signals [e.g. NDRV, NDRVB], the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection [e.g. Fig. 5B] and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection [e.g. Fig. 5A; paragraph 032 recites “Reconfigurable inductance 491 may be configured as shown in FIGS. 5A and 5B. In FIG. 5A, NDRV is high and switches 510 and 512 are closed, and NDRVB (NDRV bar, or the inverse of NDRV) is low and switch 511 is open. Accordingly, in this configuration, inductors 501 and 502 are in parallel. In FIG. 5B, NDRVB is high and switch 511 is closed, and NDRV is low and switches 510 and 512 are open. Accordingly, in this configuration, inductors 501 and 502 are in series”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Odaohhara by wherein the variable inductor device includes: a plurality of inductors, and a switching unit that is configured to be opened and closed according to the one or more second control signals, the switching unit being in a first state sets a connection configuration of the plurality of inductors to be in a series connection and the switching unit being a second state sets the connection configuration of the plurality of inductors to be in a parallel connection as taught by Lerdworatawee in order of being able to reduce noise and improve efficiency performance over a wide bandwidth range, paragraph 03.
Regarding claim 11, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is configured to generate the one or more first control signals that control the switching device using one of a pulse frequency modulation (PFM) control method and a pulse width modulation (PWM) control method [e.g. paragraphs 054 – 0 55 recite “A well-known operation mode called an intermittent mode is employed in order to reduce the light-load loss of a PWM switching regulator. The intermittent mode is also referred to as a skip mode, a burst mode, or a sleep mode, for example. The intermittent mode is usually used together with a PWM mode so that the PWM mode is used in the heavy load state, and the intermittent mode is used in the light load state. In the intermittent mode, the On period of the high-side FET is maintained to be constant while ignoring several control pulses during the PWM mode, and the Off period of the high-side FET is controlled so that an output voltage falls within the range of an upper limit and a lower limit. In a switching regulator employing the intermittent mode, it is possible to reduce the switching loss by decreasing the substantial switching frequency to be lower than that in the PWM mode. In this case, the ideas of the present invention regarding the switching of FETs illustrated in FIGS. 2 and 4 and the switching of inductors illustrated in FIGS. 6 and 7 can be applied to the intermittent mode. Although the PWM mode DC/DC converter has been described by way of an example, the present invention can be applied to a PFM mode DC/DC converter. Examiner note: There’s a necessary threshold for changing the light and heavy load states, paragraph 030].
Regarding claim 12, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is configured to generate the one or more first control signals that control the switching device using the PFM control method when the load current is lower than a threshold, and to generate the one or more first control signals that control the switching device using the PWM control method when the load current is higher than the threshold [e.g. paragraphs 054 – 055 as stated above with respect to claim 11. Examiner note: There’s a necessary threshold for changing the light and heavy load states, paragraph 030].
Regarding claim 13, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is further configured to generate the one or more second control signals that control the variable inductor device to have a first inductance value [e.g. switch OFF, wherein both inductors 355, 357 are used] when the load current is less than a threshold value [e.g. light load], and to have a second inductance [e.g. switch ON, only inductor 357 is used] smaller than the first inductance value when the load current is higher than the threshold value [e.g. paragraphs 054 – 055 recite “A well-known operation mode called an intermittent mode is employed in order to reduce the light-load loss of a PWM switching regulator. The intermittent mode is also referred to as a skip mode, a burst mode, or a sleep mode, for example. The intermittent mode is usually used together with a PWM mode so that the PWM mode is used in the heavy load state, and the intermittent mode is used in the light load state. In the intermittent mode, the On period of the high-side FET is maintained to be constant while ignoring several control pulses during the PWM mode, and the Off period of the high-side FET is controlled so that an output voltage falls within the range of an upper limit and a lower limit. In a switching regulator employing the intermittent mode, it is possible to reduce the switching loss by decreasing the substantial switching frequency to be lower than that in the PWM mode. In this case, the ideas of the present invention regarding the switching of FETs illustrated in FIGS. 2 and 4 and the switching of inductors illustrated in FIGS. 6 and 7 can be applied to the intermittent mode. Although the PWM mode DC/DC converter has been described by way of an example, the present invention can be applied to a PFM mode DC/DC converter. Examiner note: There’s a necessary threshold for changing the light and heavy load states, paragraph 030].
Regarding claim 14, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is further configured to generate the one or more first control signals and the one or more second control signals to control the voltage converter in a first mode when the load current is lower than a threshold value [e.g. light load], and to control the voltage converter in a second mode when the load current is higher than the threshold value [e.g. heavy load], wherein the switching device is controlled by a pulse frequency modulation (PFM) control method in the first mode [e.g. paragraphs 054 – 055], and controlled by a pulse width modulation (PWM) control method in the second mode [e.g. paragraphs 054 – 055], and wherein the variable inductor device has a first inductance value in the first mode [e.g. during light load both inductors are connected in series] and has a second inductance value that is smaller than the first inductance value in the second mode [e.g. during heavy load only inductor 357 is used].
Regarding claim 15, Odaohhara [e.g. Fig. 7] discloses wherein the switching unit [e.g. 353] that is controlled according to the one or more second control signals from the control circuit [e.g. output of 351] and couples at least one of the plurality of inductors between the switching device and the output line [e.g. when conducting couples 357 to 103, 105 and output line 117; paragraph 053 above with respect to claims 1 – 2].
Regarding claim 19, Odaohhara [e.g. Fig. 7] discloses wherein the control circuit is further configured to: determine the one or more first control signals to switch a control mode [e.g. heavy load mode / light load mode] for the switching device according to the load current [e.g. Paragraph 030 recites “The driver control circuit 169 determines whether a present load state is a heavy load state or a light load state based on the output of the operational amplifier 159”]; after the control mode for the switching device is switched [e.g. after it is determined that the state is light load after heavy load], determine a specific inductance value that increases an efficiency of the voltage converter [e.g. by switching (353) ON (heavy load) and OFF (light load), the efficiency is improved by minimizing ripples according to the inductance value by by-passing the inductance 355 when during heavy load and connected in series both inductors 355,357 during light load”]; and change an inductance value of the variable inductor device to the specific inductance value [e.g. paragraph 053 recites “The driver control circuit 351 …turns on the FET 353 so that only the inductor 357 contributes to the reduction of the ripple voltage at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the heavy-load FETs 103 and 105, respectively, based on the output of the operational amplifier 159. The driver control circuit 351 …turns off the FET 353 at the time of switching the high-side switching circuit 151 and the low-side switching circuit 153 to be connected to the light-load FETs 107 and 109, respectively. By doing so, when the switching frequency is decreased, the total inductance value of the inductors 355 and 357 can be contributed to the reduction of the ripple voltage”].
Regarding claim 21, Odaohhara [e.g. Fig. 7] discloses wherein: the variable inductor device includes a first inductor [e.g. 357], a second inductor [e.g. 355] connected in series with the first inductor, and a switching element [e.g. 353] configured to switch the inductance value of the variable inductor device, and the switching element is connected between the second inductor [e.g. source (left) terminal of 353] and the output line [e.g. drain (right) terminal of 353].
Claim(s) 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Odaohhara in view of Lerdworatawee and further in view of US Pub. No. 2017/0141752; (hereinafter Hino), cited by Applicant(s).
Regarding claim 5 and claim 17, Odaohhara fails to disclose wherein the variable inductor device includes the plurality of inductors that are built inside a substrate on which the switching unit is mounted.
Hino [e.g. Fig. 11 - 12] teaches wherein the variable inductor device includes the plurality of inductors [e.g. 19] that are built inside a substrate [e.g. paragraph 0122 recites “the first and second no-electrode-forming areas A and B are set such that the exterior shape of the inductor components 19 will be arranged inside the first and second no-electrode-forming areas A and B. With regard to the dielectric layer 141 near the top face 14a of the first substrate 14 on which the mounting electrodes 23 are formed”] on which the switching unit is mounted [e.g. paragraph 0131 recites “Other circuit elements may further be arranged in the RF component 10... an antenna duplexer such as a switch IC may be mounted in the RF component 10”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Odaohhara by wherein the variable inductor device includes the plurality of inductors that are built inside a substrate on which the switching unit is mounted as taught by Hino in order of being able to effectively suppressing the deterioration of the characteristics of the inductor, paragraph 0123.
Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Odaohhara in view of Lerdworatawee and further in view of US Patent No. 10,243,449.
Regarding claim 6 and claim 18, Odaohhara fails to disclose wherein the switching unit includes back-to-back connected field effect transistors.
Young [e.g. Fig. 2A] teaches wherein the switching unit includes back-to-back connected field effect transistors [e.g. Q3-Q4].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Odaohhara by wherein the switching unit includes back-to-back connected field effect transistors as taught by Hino in order of being able to enhance circuit performance in different operational modes, col. 2, lines 15 - 24.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 9 is allowed.
Claim(s) 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the inductance value of the variable inductor device is the first value in the first mode and the second value that is smaller than the first value in the second mode and the intermediate mode”.
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the variable inductor device has a first inductance value in the first mode and has a second inductance value that is smaller than the first inductance value in the second mode and the intermediate mode”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
Prosecution Insights