DETAILED ACTION
Claims 1-5, 8-15 and 18-21 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8, 10-15, 18 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (U.S. PGPub No. 2006/0026594) in view of Mukherjee et al. (U.S. Patent No. 11500779) in view of Shah et al. (U.S. Patent No. 9529594).
Claim 1
Yoshida (2006/0026594) teaches:
A storage device comprising:
a first storage medium; FIG. 1 L1 caches 18, 19
a second storage medium; FIG. 1 L2 cache 20
a processor configured to: FIG. 1 L1 cache control unit 24
receive from a computing device a first request for first data, the first request for data including a first indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as a load instruction, a store instruction, an instruction code including a prefetch instruction and IID needed for the execution; P. 0097 load and store instructions are referred to as demand requests; P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand
select a first mode of processing of the first request based on the first indicia; P. 0097 load instructions transfer data from the memory into register 13, while store instructions write data from register 13 into memory 21
based on selecting the first mode of processing of the first request, transmit the first data to the computing device; P. 0100 if a cache hit occurs and it is a load instruction, the data is supplied to the register 13
receive from the computing device a second request for second data, the second request for second data including a second indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as an instruction code including a prefetch instruction and IID needed for the execution; P. 0099 L2 prefetch request for bringing data into the L2 cache 20; P. 0131 a L1 prefetch request (request B) may follow a demand request A in a program sequence
select a second mode of processing of the second request based on the second indicia; and P. 0098 a prefetch instruction (software prefetch) is a program instruction for bringing data onto the L1 cache or the L2 cache 20; P. 0078
Yoshida does not explicitly teach selecting a response for a second mode of processing based on the request data’s location.
Mukherjee (11500779) teaches:
based on selecting the second mode of processing of the second request, determine a response type for a second response based on a location of the second data, Col. 16 line 58 – Col. 17 line 15 and FIG. 6 The prefetch request for address X is a cache miss with respect to the L1 cache 615 and L2 cache 620, vector prefetch unit 630 will send the vector prefetch request with a tuple over the interconnection network 112 to the external memory system 113 [location] to obtain the data. The missed prefetch request for address X is stored in an entry in the MASU 625 [response]
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida with selecting a response for a second mode of processing based on the request data’s location taught by Mukherjee
The motivation being to process outstanding cache misses in an efficient manner (see Mukherjee Col. 4 lines 51-53)
The systems of Yoshida and Mukherjee do not explicitly teach setting a field value of the second response and transmitting it to the computing device.
Shah (9529594) teaches:
wherein based on determining that the location of the second data is the second storage medium, set a field value of the second response and transmit the second response to the computing device. Col. 5 line 66 – Col. 6 line 9 as a result of an instruction cache miss [location in second storage], a miss request [second response] may be generated; Col. 8 line 60 – Col. 9 line 26 and FIG. 2 tag information 220 [field value] is used to identify and/or track different miss requests, and may accompany a miss request through the cache/memory hierarchy, and be returned to instruction miss buffer 110
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida and Mukherjee with setting a field value of the second response and transmitting it to the computing device taught by Shah
The motivation being to identify and/or track different miss requests (see Shah Col. 8 line 60 – Col. 9 line 26)
The systems of Yoshida, Mukherjee and Shah are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yoshida and Mukherjee with Shah to obtain the invention as recited in claim 1-10.
Claim 2
Yoshida (2006/0026594) teaches:
The storage device of claim 1, wherein the first indicia includes a value for indicating the first request as a load or store request. P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand; P. 0097 load and store instructions are referred to as demand requests
Claim 3
Yoshida (2006/0026594) teaches:
The storage device of claim 2, wherein the processor is configured to select the first mode of processing based on the first indicia indicating the first request as the load or store request. P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand; P. 0097 load instructions transfer data from the memory into register 13, while store instructions write data from register 13 into memory 21
Claim 4
Yoshida (2006/0026594) teaches:
The storage device of claim 1, wherein the second indicia includes a value for indicating the second request as a prefetch request. P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as a load instruction, a store instruction, an instruction code including a prefetch instruction and IID needed for the execution
Claim 5
Yoshida (2006/0026594) teaches:
The storage device of claim 4, wherein the processor is configured to select the second mode of processing based on the second indicia indicating the second request as the prefetch request. P. 0098 a prefetch instruction (software prefetch) is a program instruction for bringing data onto the L1 cache or the L2 cache 20
Claim 8
Mukherjee (11500779) teaches:
The storage device of claim 5, wherein, based on the processor selecting the second mode of processing, the processor is configured to retrieve the second data from the second storage medium […] Col. 16 line 58 – Col. 17 line 15 vector prefetch unit 630 will send the vector prefetch request with a tuple over the interconnection network 112 to the external memory system 113 to obtain the data; Col. 18 lines 13-25 receiving 740 the data in at least one response message from the next memory level
Yoshida (2006/0026594) teaches:
retrieve the second data from the second storage medium to the first storage medium. P. 0105 The data response returned in this way is stored in L2 cache 20. Following this, the data response is stored in the corresponding L1MIB 26 and the L1 cache control unit 24 performs the writing in the L1 data cache 19
Claim 10
Shah (9529594) teaches:
The storage device of claim 1, wherein the processor is configured to: determine priority of the first request relative to the second request; and Col. 9 line 39 – Col. 10 line 14 if both a pre-fetch miss request and a demand miss request are being made, the demand miss request may be given priority
process the first request based on the determined priority. Col. 6 lines 13-51 A miss request for instructions not present in L1 cache 140 may be serviced, if one or more instructions targeted by a miss request are present within L2 cache 150, circuit logic forwards the requested instructions from L2 cache 150 to L1 cache 140 in order to fulfill the miss request
Claim 11
Yoshida (2006/0026594) teaches:
A method comprising: receiving from a computing device a first request for first data, the first request for data including a first indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as a load instruction, a store instruction, an instruction code including a prefetch instruction and IID needed for the execution; P. 0097 load and store instructions are referred to as demand requests; P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand
selecting a first mode of processing of the first request based on the first indicia; P. 0097 load instructions transfer data from the memory into register 13, while store instructions write data from register 13 into memory 21
based on selecting the first mode of processing of the first request, transmitting the first data to the computing device; P. 0100 if a cache hit occurs and it is a load instruction, the data is supplied to the register 13
receiving from the computing device a second request for second data, the second request for second data including a second indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as an instruction code including a prefetch instruction and IID needed for the execution; P. 0099 L2 prefetch request for bringing data into the L2 cache 20; P. 0131 a L1 prefetch request (request B) may follow a demand request A in a program sequence
selecting a second mode of processing of the second request based on the second indicia; and P. 0098 a prefetch instruction (software prefetch) is a program instruction for bringing data onto the L1 cache or the L2 cache 20; P. 0078
Yoshida does not explicitly teach selecting a response for a second mode of processing based on the request data’s location.
Mukherjee (11500779) teaches:
based on selecting the second mode of processing of the second request, determining a response type for a second response based on a location of the second data, Col. 16 line 58 – Col. 17 line 15 and FIG. 6 The prefetch request for address X is a cache miss with respect to the L1 cache 615 and L2 cache 620, vector prefetch unit 630 will send the vector prefetch request with a tuple over the interconnection network 112 to the external memory system 113 [location] to obtain the data. The missed prefetch request for address X is stored in an entry in the MASU 625 [response]
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida with selecting a response for a second mode of processing based on the request data’s location taught by Mukherjee
The motivation being to process outstanding cache misses in an efficient manner (see Mukherjee Col. 4 lines 51-53)
The systems of Yoshida and Mukherjee do not explicitly teach setting a field value of the second response and transmitting it to the computing device.
Shah (9529594) teaches:
wherein based on determining that the location of the second data is a second storage medium, set a field value of the second response and transmit the second response to the computing device. Col. 5 line 66 – Col. 6 line 9 as a result of an instruction cache miss [location in second storage], a miss request [second response] may be generated; Col. 8 line 60 – Col. 9 line 26 and FIG. 2 tag information 220 [field value] is used to identify and/or track different miss requests, and may accompany a miss request through the cache/memory hierarchy, and be returned to instruction miss buffer 110
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida and Mukherjee with setting a field value of the second response and transmitting it to the computing device taught by Shah
The motivation being to identify and/or track different miss requests (see Shah Col. 8 line 60 – Col. 9 line 26)
The systems of Yoshida, Mukherjee and Shah are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yoshida and Mukherjee with Shah to obtain the invention as recited in claim 11-20.
Claim 12
Yoshida (2006/0026594) teaches:
The method of claim 11, wherein the first indicia includes a value for indicating the first request as a load or store request. P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand; P. 0097 load and store instructions are referred to as demand requests
Claim 13
Yoshida (2006/0026594) teaches:
The method of claim 12 further comprising: selecting the first mode of processing based on the first indicia indicating the first request as the load or store request. P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand; P. 0097 load instructions transfer data from the memory into register 13, while store instructions write data from register 13 into memory 21
Claim 14
Yoshida (2006/0026594) teaches:
The method of claim 11, wherein the second indicia includes a value for indicating the second request as a prefetch request. P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as a load instruction, a store instruction, an instruction code including a prefetch instruction and IID needed for the execution
Claim 15
Yoshida (2006/0026594) teaches:
The method of claim 14 further comprising: selecting the second mode of processing based on the second indicia indicating the second request as the prefetch request. P. 0098 a prefetch instruction (software prefetch) is a program instruction for bringing data onto the L1 cache or the L2 cache 20
Claim 18
Mukherjee (11500779) teaches:
The method of claim 15, wherein, based on selecting the second mode of processing: retrieving the second data from the second storage medium […] Col. 16 line 58 – Col. 17 line 15 vector prefetch unit 630 will send the vector prefetch request with a tuple over the interconnection network 112 to the external memory system 113 to obtain the data; Col. 18 lines 13-25 receiving 740 the data in at least one response message from the next memory level
Yoshida (2006/0026594) teaches:
[…] retrieving the second data from the second storage medium to a first storage medium. P. 0105 The data response returned in this way is stored in L2 cache 20. Following this, the data response is stored in the corresponding L1MIB 26 and the L1 cache control unit 24 performs the writing in the L1 data cache 19
Claim 20
Shah (9529594) teaches:
The method of claim 11 further comprising: determining priority of the first request relative to the second request; and Col. 9 line 39 – Col. 10 line 14 if both a pre-fetch miss request and a demand miss request are being made, the demand miss request may be given priority
processing the first request based on the determined priority. Col. 6 lines 13-51 A miss request for instructions not present in L1 cache 140 may be serviced, if one or more instructions targeted by a miss request are present within L2 cache 150, circuit logic forwards the requested instructions from L2 cache 150 to L1 cache 140 in order to fulfill the miss request
Claim 21
Yoshida (2006/0026594) teaches:
A storage device comprising: a first storage medium; FIG. 1 L1 caches 18, 19
a second storage medium; and FIG. 1 main memory 21
a processor configured to: FIG. 1 L1 cache control unit 24
receive from a computing device a first request for first data, the first request for data including a first indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as a load instruction, a store instruction, an instruction code including a prefetch instruction and IID needed for the execution; P. 0097 load and store instructions are referred to as demand requests; P. 0116 if an instruction is a demand request, it registers a flag or IID (instruction identifier) indicative of the request on the demand
select a first mode of processing of the first request based on the first indicia; P. 0097 load instructions transfer data from the memory into register 13, while store instructions write data from register 13 into memory 21
based on selecting the first mode of processing of the first request, transmit the first data to the computing device; P. 0100 if a cache hit occurs and it is a load instruction, the data is supplied to the register 13
receive from the computing device a second request for second data, the second request for second data including a second indicia; P. 0100 and FIG. 4 L1 data cache control unit 24 receives information such as an instruction code including a prefetch instruction and IID needed for the execution; P. 0099 L2 prefetch request for bringing data into the L2 cache 20; P. 0131 a L1 prefetch request (request B) may follow a demand request A in a program sequence
select a second mode of processing of the second request based on the second indicia; P. 0098 a prefetch instruction (software prefetch) is a program instruction for bringing data onto the L1 cache or the L2 cache 20; P. 0100 L1 data cache control unit 24 receives an instruction code including a prefetch instruction and IID needed for the execution and puts instructions in the fetch queue 28
determine that a location of the second data is on the second storage medium; and P. 0104 when a cache miss occurs in the L2 cache 20, a request is issued to main memory 21 [second storage] for the data, the main memory 21 issues a data response; P. 0117 detecting a L2 cache miss with respect to an L1 prefetch request
Yoshida does not explicitly teach signaling a miss in the second mode of processing based on the request data’s being in the second storage medium.
Mukherjee (11500779) teaches:
based on selecting the second mode of processing of the second request and on determining that the location of the second data is on the second storage medium, signaling a cache miss to the computing device. Col. 16 line 58 – Col. 17 line 15 and FIG. 6 The prefetch request for address X is a cache miss with respect to the L1 cache 615 and L2 cache 620, vector prefetch unit 630 will send the vector prefetch request with a tuple over the interconnection network 112 to the external memory system 113 [location] to obtain the data. The missed prefetch request for address X is stored in an entry in the MASU 625 [signaling]
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida with signaling a miss in the second mode of processing based on the request data’s being in the second storage medium taught by Mukherjee
The motivation being to process outstanding cache misses in an efficient manner (see Mukherjee Col. 4 lines 51-53)
The systems of Yoshida and Mukherjee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yoshida with Mukherjee to obtain the invention as recited in claim 21.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (U.S. PGPub No. 2006/0026594) in view of Mukherjee et al. (U.S. Patent No. 11500779) in view of Shah et al. (U.S. Patent No. 9529594) in view of Wang et al. (U.S. PGPub No. 2020/0192715)
Claim 9
The systems of Yoshida, Mukherjee and Shah do not explicitly teach the first storage medium being volatile memory while the second storage medium is non-volatile.
Wang (2020/0192715) teaches:
The storage device of claim 8, wherein the first storage medium includes volatile memory, and the second storage medium includes non-volatile memory. P. 0096 a first level of main memory (e.g. L2 or L1 cache) is made of faster volatile memory, while a second level presented as “main memory” may be byte-addressable nonvolatile memory
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida, Mukherjee and Shah with the first storage medium being volatile memory while the second storage medium is non-volatile taught by Wang
The motivation being for efficient processing (See Wang P. 0096)
The systems of Yoshida, Mukherjee, Shah and Wang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yoshida, Mukherjee and Shah with Wang to obtain the invention as recited in claim 9.
Claim 19
The systems of Yoshida, Mukherjee and Shah do not explicitly teach the first storage medium being volatile memory while the second storage medium is non-volatile.
Wang (2020/0192715) teaches:
The method of claim 18, wherein the first storage medium includes volatile memory, and the second storage medium includes non-volatile memory. P. 0096 a first level of main memory (e.g. L2 or L1 cache) is made of faster volatile memory, while a second level presented as “main memory” may be byte-addressable nonvolatile memory
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yoshida, Mukherjee and Shah with the first storage medium being volatile memory while the second storage medium is non-volatile taught by Wang
The motivation being for efficient processing (See Wang P. 0096)
The systems of Yoshida, Mukherjee, Shah and Wang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yoshida, Mukherjee and Shah with Wang to obtain the invention as recited in claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tanamoto et al. (U.S. PGPub No. 2020/0026650) suppresses L2 prefetches after a certain amounts of hits or misses, using an indicator
Henry et al. (U.S. Patent No. 8533437) foregoing prefetching a requested cache line from system memory for the first prefetch instruction, but prefetching the requested cache line of data from the system memory for the second prefetch instruction
Kallurkar et al. (U.S. Patent No. 11847053) a prefetcher memorizing cache access streams by storing the addresses of interesting cache accesses (e.g., prefetch hits and cache misses) in a history buffer structure
McCauley et al. (U.S. PGPub No. 2014/0052927) teaches when a lower-level cache does not have the requested information, using the first miss to allocate a prefetch stream, the second miss to train the prefetch stream, and the first prefetch request (with hints) to select the address of its next prefetch request.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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