DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 2/23/2026. Claims 1-3, 6-10 and 13-14 are pending and are under examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (US 2022/0247399).
Regarding claim 1, HSU et al.’s figure 2 shows An isolated selector, comprising: at least one isolated component (222), configured to receive first data (TG) and generate isolated data (S1) according to a control signal (AG) and the first data (TG); wherein the isolated selector is coupled to a first functional circuit (101) belongs to a first power domain (101, is a separate digital signal processor/application-specific integrated circuit (paragraph 0013) which is capable of operating at a first power domain, i.e., low power consumption device) and a second functional circuit belongs to a second power domain (circuits 228 reside within the oscillator circuits which appear to be separate from the functional circuit 101 are capable of operating at a second power domain), the first functional circuit and the second functional circuit output the first data (TG) and second data (S2), respectively, the isolated selector is configured to select one of the first data and the second data to be output as output data of the isolated selector according to the control signal (AG), and when the isolated selector selects the second data (S2) to be output as the output data according to the control signal, the at least one isolated component sets the isolated data (S1) to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector; wherein the isolated selector further comprises: a selection circuit (224), configured to select one of the isolated data (S1) and the second data (S2) to be output as the output data of the isolated selector according to the control signal (AG) ;wherein the at least one isolated component comprises: an AND gate (222), coupled to the selection circuit, configured to perform an AND logic operation on the control signal (AG) and the first data (TG) to generate the isolated data (S1) of the at least one isolated component as called for in claim 1.
Regarding claim 2, wherein when the isolated selector selects the first data to be output as the output data according to the control signal, the at least one isolated component outputs the first data as the isolated data (S2) according to the control signal, to make the isolated selector transmit the first data to an output terminal of the isolated selector through the at least one isolated component.
Regarding claim 3, wherein all components within the isolated selector are capable of being integrated in a digital cell circuit of multiple digital circuit cells stored in a digital cell library.
Regarding claim 8, HSU et al.’s figure 2 shows An electronic device, comprising: a first functional circuit belongs to a first power domain (functional circuit 101, is a separate digital signal processor/application-specific integrated circuit (paragraph 0013) which is capable of operating at a first power domain, i.e., low power consumption device) configured to output first data (TG); a second functional circuit belongs to a second power domain (circuits 228 reside within the oscillator circuits which appear to be separate from the functional circuit 101 are capable of operating at a second power domain), configured to output second data (S2); a controller (circuit provides AG signal), configured to generate a control signal (AG); and an isolated selector (222, 228), coupled to the controller, the first functional circuit and the second functional circuit, configured to select one of the first data and the second data to be output as output data of the isolated selector according to the control signal, wherein the isolated selector comprises: at least one isolated component (222), coupled to the first functional circuit, configured to receive the first data and generate isolated data (S1) according to the control signal and the first data; wherein when the isolated selector selects the second data to be output as the output data according to the control signal, the at least one isolated component sets the isolated data to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector; wherein the isolated selector further comprises: a selection circuit (224), configured to select one of the isolated data (S1) and the second data (S2) to be output as the output data of the isolated selector according to the control signal (AG) ;wherein the at least one isolated component comprises: an AND gate (222), coupled to the selection circuit, configured to perform an AND logic operation on the control signal (AG) and the first data (TG) to generate the isolated data (S1) of the at least one isolated component.
Regarding claim 9, wherein when the isolated selector selects the first data to be output as the output data according to the control signal, the at least one isolated component outputs the first data as the isolated data according to the control signal, to make the isolated selector transmit the first data to an output terminal of the isolated selector through the at least one isolated component.
Regarding claim 10, wherein all components within the isolated selector are capable of being integrated in a digital cell circuit of multiple digital circuit cells stored in a digital cell library.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2022/0247399) in view of Lee et al. (USP 7,180,336).
Regarding claims 6-7 and 13-14, Hsu et al. reference discloses an isolated selector comprising all the aspects of the present invention noted in above except the selection circuit comprises: a first AND gate, coupled to the at least one isolated component, configured to perform a first AND logic operation on the isolated data and the control signal to generate a first AND logic result; a second AND gate, coupled to the second functional circuit, configured to perform a second AND logic operation on the second data and an inverted signal of the control signal to generate a second AND logic result; and an OR gate, coupled to the first AND gate and the second AND gate, configured to perform an OR logic operation on the first AND logic result and the second AND logic result to generate the output data of the isolated selector as called for in claims 6-7, 13-14.
Lee et al.’s figure 5 shows a selector comprising a first AND gate (542), coupled to the at least one isolated component, configured to perform a first AND logic operation on the isolated data and the control signal to generate a first AND logic result; a second AND gate (541), coupled to the second functional circuit, configured to perform a second AND logic operation on the second data and an inverted signal of the control signal to generate a second AND logic result; and an OR gate (543), coupled to the first AND gate and the second AND gate, configured to perform an OR logic operation on the first AND logic result and the second AND logic result to generate the output data of the isolated selector. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Lee et al.’s selector in Hsu et al.’s circuit arrangement for the purpose of selecting a desired output signal as taught by Lee et al. reference.
Response to Arguments
Applicant's arguments filed 2/23/2026 have been fully considered but they are not persuasive. Regarding the rejection of claims 1-3 and 8-10 as being anticipated by Hsu et al. (US 2022/0247399), applicant argues that according to the disclosure of Hsu, the oscillator circuit 120 within the reliability detection device 100 is configured to detect degradation of the functional circuit 101. The applicant believes that those skilled in this art should regard the functional circuit 101 and the oscillator circuit 120 (e.g. the inverter 228 therein) as belonging to the same power domain. Thus, the applicant believes that Hsu fails to teach the limitation "the first functional circuit (which outputs the first data associated with the isolated data) belongs to a first power domain, the second functional circuit (which outputs the second data) and the isolated belongs to a second power domain".
Examiner respectfully disagrees. Hsu’s paragraph 0013 discloses a first functional circuit (101) can be a separate digital signal processor/application-specific integrated circuit which is capable of operating at a first power domain, i.e., low power consumption device and a second functional circuit belongs to a second power domain (circuits 228 reside within the oscillator circuits which appear to be separate from the functional circuit 101 are capable of operating at a second power domain). Thus, the limitation of the first functional circuit belongs to a first power domain and the second functional circuit belongs to a second power domain is fully met. The rejection is deemed proper. Claims 1-3 and 8-10 remain rejected.
Claims 6-7 and 13-14 depends on claims 1 and 8 respectively remain remains for the reasons set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2842
4/12/2026
Prosecution Insights