DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a capacitive structure, and a control logic circuit, coupled to the capacitive structure and comprising a plurality of switch groups, wherein each of the plurality of switch groups comprises a first switch circuit and a second switch circuit, and each of the first switch circuit and the second switch circuit comprises: a first terminal, wherein the first terminal of the first switch circuit is configured to receive the positive reference voltage through a first shielding layer of the CDAC, a second terminal, configured to be coupled to the capacitive structure; and a control terminal, configured to receive one of a plurality of turn-on signals through a first metal layer of the CDAC, wherein the capacitive structure is located at least in a second metal layer of the CDAC, and in a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, wherein the vertical direction is vertical to plane directions of the first metal layer, the second metal layer, the first shielding layer and the second shielding layer.
Claim 2 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 2 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein each of the plurality of switch groups further comprises a third switch circuit, and the third switch circuit comprises: a first terminal, configured to receive a common mode voltage, wherein the common mode voltage, the positive reference voltage and the negative reference voltage are different from each other; a second terminal, configured to be coupled to the capacitive structure; and a control terminal, configured to receive another of the plurality of turn-on signals through the first metal layer.
Claim 3 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a third shielding layer, coupled to the first terminal of the third switch circuit, and configured to receive the common mode voltage and shield the capacitive structure and the control logic circuit, wherein in the vertical direction, the third shielding layer is located between the first metal layer and the second metal layer.
Claim 4 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 3 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein one of the first switch circuit, the second switch circuit and the third switch circuit of each of the plurality of switch groups is turned on according to the plurality of turn-on signals, and the other two of the first switch circuit, the second switch circuit and the third switch circuit are turned off according to the plurality of turn-on signals.
Claim 5 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein N first switch circuits of N of the plurality of switch groups are turned on or turned off synchronously, N second switch circuits of the N of the plurality of switch groups are turned on or turned off synchronously, and N third switch circuits of the N of the plurality of switch groups are turned on or turned off synchronously; other 2N first switch circuits of 2N of the plurality of switch groups are turned on or turned off synchronously, other 2N second switch circuits of the 2N of the plurality of switch groups are turned on or turned off synchronously, and other 2N third switch circuits of the 2N of the plurality of switch groups are turned on or turned off synchronously; and yet other 4N first switch circuits of 4N of the plurality of switch groups are turned on or turned off synchronously, yet other 4N second switch circuits of the 4N of the plurality of switch groups are turned on or turned off synchronously, and yet other 4N third switch circuits of the 4N of the plurality of switch groups are turned on or turned off synchronously, wherein N is a positive integer.
Claim 6 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a first via extending along the vertical direction, wherein the second terminals of the first switch circuit and the second switch circuit are coupled to the capacitive structure through the first via.
Claim 7 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a third metal layer of the CDAC, wherein in the vertical direction, the third metal layer is located above the second metal layer, and the second metal layer and the third metal layer are coupled to each other through a second via extending along the vertical direction.
Claim 8 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 8 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a signal receiving layer and a third via, wherein in the vertical direction, the signal receiving layer is located above the first metal layer and coupled to the first metal layer through the third via, and is configured to receive the plurality of turn-on signals from an external circuit and transmit the plurality of turn-on signals to the first metal layer through the third via.
Claim 9 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: forming a control logic circuit comprising a plurality of switch groups, comprising: forming a plurality of first switch circuits, wherein a first terminal of each of the plurality of first switch circuits is configured to receive a positive reference voltage through a first shielding layer of the CDAC, and a control terminal of each of the plurality of first switch circuits is configured to receive one of a plurality of turn-on signals through a first metal layer of the CDAC; and forming a plurality of second switch circuits, wherein a first terminal of each of the plurality of second switch circuits is configured to receive a negative reference voltage through a second shielding layer of the CDAC, and a control terminal of each of the plurality of second switch circuits is configured to receive another of the plurality of turn-on signals through the first metal layer; and forming a capacitive structure, wherein the capacitive structure is located at least in a second metal layer of the CDAC and coupled to a plurality of second terminals of the plurality of first switch circuits and the plurality of second switch circuits, wherein two terminals of the capacitive structure are configured to respectively receive the positive reference voltage and the negative reference voltage, wherein in a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, and the vertical direction is vertical to plane directions of the first metal layer, the second metal layer, the first shielding layer and the second shielding layer.
Claim 10 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 10 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein forming the control logic circuit comprising the plurality of switch groups further comprises: forming a plurality of third switch circuits, wherein a first terminal of each of the plurality of third switch circuits is configured to receive a common mode voltage through a third shielding layer, a second terminal of each of the plurality of third switch circuits is coupled to the capacitive structure, and a control terminal of each of the plurality of third switch circuits is configured to receive yet another of the plurality of turn-on signals through the first metal layer, wherein the third shielding layer is located between the first metal layer and the second metal layer, and the common mode voltage, the positive reference voltage and the negative reference voltage are different from each other.
Claim 11 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 11 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: forming the capacitive structure comprises: forming the capacitive structure in the second metal layer and a third metal layer of the CDAC, wherein in the vertical direction, the third metal layer is located above the second metal layer, and the second metal layer and the third metal layer are coupled to each other through a via extending along the vertical direction.
Claim 12 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 12 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: forming a signal receiving layer, so as to receive the plurality of turn-on signals form an external circuit and transmit the plurality of turn-on signals to the second metal layer, wherein in the vertical direction, the signal receiving layer is located above the second metal layer and coupled to the second metal layer through a via extending along the vertical direction.
Claim 13 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 13 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a capacitive digital-to-analog converter (CDAC), comprising a capacitive structure and a control logic circuit coupled to each other, wherein two terminals of the capacitive structure are configured to respectively receive a positive reference voltage and a negative reference voltage for sampling an input signal and generating a first signal and a second signal, and the control logic circuit is configured to adjust the first signal and the second signal based on a plurality of turn-on signals; a comparator, coupled to the CDAC and configured to generate a decision signal based on the first signal and the second signal; and a logic decision circuit, coupled to the CDAC and the comparator, and configured to generate the plurality of turn-on signals and an output signal based on the decision signal, wherein the control logic circuit is configured to receive the positive reference voltage and the negative reference voltage respectively through a first shielding layer and a second shielding layer of the CDAC, and receive the plurality of turn-on signals through a first metal layer of the CDAC, the capacitive structure is located at least in a second metal layer of the CDAC, and in a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, wherein the vertical direction is vertical to plane directions of the first metal layer, the second metal layer, the first shielding layer and the second shielding layer.
Claim 14 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 14 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the logic decision circuit is further configured to receive a common mode voltage, wherein the common mode voltage, the positive reference voltage and the negative reference voltage are different from each other.
Claim 15 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a third shielding layer, the third shielding layer is configured to receive the common mode voltage and shield the capacitive structure and the control logic circuit, wherein in the vertical direction, the third shielding layer is located between the first metal layer and the second metal layer.
Claim 16 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 15 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the logic decision circuit comprises a plurality of switch groups, each of the plurality of switch groups comprises a first switch circuit configured to receive the positive reference voltage, a second switch circuit configured to receive the negative reference voltage, and a third switch circuit configured to receive the common mode voltage, wherein one of the first switch circuit, the second switch circuit and the third switch circuit of each of the plurality of switch groups is turned on according to the plurality of turn-on signals, and the other two of the first switch circuit, the second switch circuit and the third switch circuit are turned off according to the plurality of turn-on signals.
Claim 17 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 16 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein N first switch circuits of N of the plurality of switch groups are turned on or turned off synchronously, N second switch circuits of the N of the plurality of switch groups are turned on or turned off synchronously, and N third switch circuits of the N of the plurality of switch groups are turned on or turned off synchronously; other 2N first switch circuits of 2N of the plurality of switch groups are turned on or turned off synchronously, other 2N second switch circuits of the 2N of the plurality of switch groups are turned on or turned off synchronously, and other 2N third switch circuits of the 2N of the plurality of switch groups are turned on or turned off synchronously; and yet other 4N first switch circuits of 4N of the plurality of switch groups are turned on or turned off synchronously, yet other 4N second switch circuits of the 4N of the plurality of switch groups are turned on or turned off synchronously, and yet other 4N third switch circuits of the 4N of the plurality of switch groups are turned on or turned off synchronously, wherein N is a positive integer.
Claim 18 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 13 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: a first via extending along the vertical direction, wherein the control logic circuit is coupled to the capacitive structure through the first via.
Claim 19 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 19 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the capacitive structure is located in the second metal layer and a third metal layer of the CDAC, wherein in the vertical direction, the third metal layer is located above the second metal layer, and the second metal layer and the third metal layer are coupled to each other through a second via extending along the vertical direction.
Claim 20 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over claim 20 of co-pending Application No. 18/780,509 (US 2025/0175187)). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 1 of the US 2025/0175187 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the CDAC further comprises a signal receiving layer and a third via, wherein in the vertical direction, the signal receiving layer is located above the first metal layer and coupled to the first metal layer through the third via, and is configured to receive the plurality of turn-on signals from the logic decision circuit and transmit the plurality of turn-on signals to the first metal layer through the third via.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845