Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 9, 10, 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mathur (US 11424716 B2, cited by the applicant) in view of Siddamurthy (US 11303480 B2), hereafter referred to as “Mathur” and “Siddamurthy”, respectively.
Regarding claims 1, 3-6, 9, 10, 12, 13, and 15, in the embodiment of Fig. 5, Mathur discloses:
A receiver circuitry (Fig. 5, receiver device 150 with regards to Fig. 4 as part of the non-volatile memory device 104 depicted in FIGS. 1A-B, 2, and 3A-B, per column 15 lines 57-64) in a storage device (storage device 120 and/or storage system 204) to provide an interface between a controller (FIGS. 1A-B, 2, and 3A-B, controller 102) and a memory device (non-volatile memory device 104) in the storage device, the receiver circuitry comprises:
an amplifier to operated in a first stage (Fig. 5, Current Source, First, and Second stage circuits 402, 404 and 406 may form the first stage of the amplifier, per claims 1 and 12) and receive an input (IO supply voltage 420) and produce a high gain at high and low speeds (receiver device 150 may be designed as a high speed differential amplifier with a high gain second stage and support high speed operations per column 7 lines 48-55), wherein complementary inputs into the amplifier provide a high input common mode range (column 8 lines 1-3, receiver device 150 may use native NMOS to give a near rail to rail input common mode range, per claim 4); and
a skew balanced level down shifter to operate in a third stage (Fig. 5, duty cycle balancer circuit 408) to correct a duty cycle error resulting from shifting a signal across domains (the duty cycle balancer may be configured to balance a rise and fall delay skew across PVT to maintain a tighter duty cycle), wherein the skew balanced level down shifter receives two signals with delay between the signals (column 3 lines 9-10, the duty cycle balancer may be configured to balance a rise and fall delay skew), wherein a first signal is an inverted signal of a second signal (PMOS transistors MP8 and NMOS transistors MN10 per column 17 lines 53-56, it is known in the art that PMOS transistors inherently conducts when a positive voltage is applied to the gate while NMOS transistors inherently conducts when a negative voltage is applied to the gate, thereby receiving inverted signals per claim 9), and wherein the skew balanced level down shifter balances a skew, negates an impact of the skew (column 3 lines 9-11, the duty cycle balancer may be configured to balance a rise and fall delay skew across PVT to maintain a tighter duty cycle), and level down shifts the signal to a core voltage (column 1 lines 24-26, receivers (per the background of the invention) can provide a digital output that is down converted to a core voltage signal (VDD) level at an output voltage signal (VOUT) per claim 10)..
However, Mathur is silent and teaching an equalizer to operate in a second stage, wherein the equalizer includes a resistor and a capacitor, and the equalizer increases the gain at high speeds and producing a high gain with gain booster cells and a complementary input folded cascade structure, wherein peak frequency in the equalizer is tunable through the capacitor.
Siddamurthy teaches:
an equalizer (Fig. 1, Continuous Time Linear Equalizer (CTLE) 24), wherein the equalizer includes a resistor and a capacitor (RS and CS), and the equalizer increases the gain at high speeds (The parallel combination of resistor RS and capacitor CS can boost the gain of high frequency components of a received signal per column 1 lines 60-62) and producing a high gain with gain booster cells (Fig. 3, cross-couple booster 330 can facilitate further boosting of the gain, per column 7 lines 52-56) and a complementary input folded cascade structure (Fig. 3, derivative path 320 of the folded cascode amplifier wherein cross-couple booster 330 is connected).
It would have been obvious to modify the receiver circuitry as taught by Mathur (Fig. 5) to further include an equalizer, such as the equalizer taught by Siddamurthy (Fig. 1) to treat received signals, which are likely affected by inter-symbol interference while traversing through high-speed communication channels (per column 1, lines 24-27). Furthermore it would be obvious to include a resistor and capacitor in the equalizer taught by Siddamurthy (Fig. 1, RS and CS) to boost the gain of high frequency components o f a received signal (per column 1 lines 60-62), thereby suggesting such a combination. It would further be obvious to replace the first stage of the amplifier taught by Mathur with the folded cascode amplifier with boosters, as taught by Siddamurthy (Fig. 3) to facilitate further gain boosting (per column 7 lines 52-56), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 2, 7, 8, 11, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2, 7, 8, 11, and 14:
the cited prior art of record, Mathur (US 11424716 B2, cited by the applicant), either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
“an input of approximately 200 milli-Volts and produces the high gain in a first stage” per claim 2,
“peak frequency in the equalizer is tunable through the capacitor” per claim 7,
“ the second stage (comprising the equalizer) provides a low impedance path through the resistor to improve a bandwidth of a first stage” per claims 8 and 14,
“the skew balanced level down shifter comprises a differential level down shifter with a skew balancer and duty cycle balancers” per claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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