Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20220180809 A1), in view of Sugimoto (US 20200177143 A1).
Regarding independent claim 1, Wang teaches a semiconductor device comprising: a first transistor including a first gate electrode (Fig. 6, T7, G7; [0084], "The seventh transistor T7 has a gate electrode G7 electrically connected to the reset signal line 62…"); and a second transistor including a second gate electrode electrically connected to the first gate electrode (Fig. 6, T1, G1; [0078], "The first transistor T1 has the gate electrode G1 electrically connected to the reset signal line 62...") and a source electrode electrically connected to a drain electrode of the first transistor (Fig. 6, S1, D7; [0078], "The first transistor T1 has…a source electrode Si electrically connected to the initializiation voltage line 66..", [0084], "The seventh drain region 205g may be electrically connected to the initialization voltage line 66…").
However, Wang does not teach wherein the first transistor includes a first channel width and a first gate length, the second transistor includes a second channel width and a second gate length, and a value obtained by dividing the second channel width by the second gate length is greater than or equal to a value obtained by dividing the first channel width by the first gate length.
However, in the same field of endeavor, Sugimoto teaches wherein the first transistor includes a first channel width and a first gate length ([0036], "...the gate width W1 of the transistor 91 by the gate length L1 of the transistor 91."), the second transistor includes a second channel width and a second gate length ([0036], "...the gate width (channel width) W2 of the transistor 92 by the gate length (channel length) L2 of the transistor 92…"), and a value obtained by dividing the second channel width by the second gate length is greater than or equal to a value obtained by dividing the first channel width by the first gate length ([0036], "The value (width-to-length (W/L) value) W2/L2 obtained by dividing the gate width (channel width) W2 of the transistor 92 by the gate length (channel length) L2 of the transistor 92 is set K (K is a real number larger than 1) times greater than the W/L value W1/L1 obtained by dividing the gate width W1 of the transistor 91 by the gate length L1 of the transistor 91.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor device of Wang with the channel width and gate length of Sugimoto so that "the differential amplifier circuits can be appropriately adjusted to prevent non-linear operation", (Sugimoto, [0003]).
Regarding dependent claim 2, Wang, as previously modified by Sugimoto, teaches the semiconductor device according to claim 1. Sugimoto further teaches wherein the first gate length is the same as the second gate length ([0036], "As described above, the gate length L2 may be equal to the gate length L1.").
Regarding dependent claim 3, Wang, as previously modified by Sugimoto, teaches the semiconductor device according to claim 2. Sugimoto further teaches wherein the second channel width is N times the first channel width ([0036], "The value (width-to-length (W/L) value) W2/L2 obtained by dividing the gate width (channel width) W2 of the transistor 92 by the gate length (channel length) L2 of the transistor 92 is set K (K is a real number larger than 1) times greater than the W/L value W1/L1 obtained by dividing the gate width W1 of the transistor 91 by the gate length L1 of the transistor 91.", (Since the ratio of W2/L2 is K times larger than the ratio of W1/L1, and L1=L2, W2 = KL1)).
Regarding dependent claim 4, Wang, as previously modified by Sugimoto, teaches the semiconductor device according to claim 1, and further teaches further comprising an active layer (Fig. 8; [0076], "The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be formed along an active layer as shown in FIG. 8."), wherein the active layer includes one pattern having the first channel width and the second channel width (Fig. 8, Since the active layer has two different widths, this could be combined with the channel widths of Sugimoto to produce an active layer having two channel widths.).
Regarding dependent claim 5, Wang, as previously modified by Sugimoto, teaches the semiconductor device according to claim 4, and further teaches wherein the active layer includes a poly-silicon ([0077], "The active layer may contain, for example, polysilicon…").
Regarding dependent claim 6, Wang, as previously modified by Sugimoto, teaches the semiconductor device according to claim 1, and further teaches wherein a source electrode of the first transistor is electrically connected to a voltage supply line, and is supplied with a ground voltage from the voltage supply line (Fig. 6, 66, S1, S7; [0075], "...an initialization voltage line 66 for transmitting an initialization voltage Vint…").
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 6781459 B1), in view of Wang (US 20220180809 A1) and Sugimoto (US 20200177143 A1).
Regarding dependent claim 7, Brown teaches an OP-AMP (Col. 7, Lines 2-5, "The NTP circuit can be substituted for an operational amplifier (op amp) or other types of differential amplifiers…",). However, Brown does not teach comprising: a plurality of the semiconductor devices according to claim 1.
However, as previously combined, Wang and Sugimoto teach the semiconductor devices according to claim 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the OP-AMP of Brown with the semiconductor devices as described by the combination of Wang and Sugimoto so as "to provide a circuit that can be used in a wide range of applications", (Brown, Col. 1, Lines 29-30).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 6781459 B1), in view of Wang (US 20220180809 A1), Sugimoto (US 20200177143 A1), and Moue (US 20220046197 A1).
Regarding dependent claim 8, Brown, as previously modified by Wang and Sugimoto, teaches the OP-AMP according to claim 7, and further teaches wherein the plurality of the semiconductor devices includes a first semiconductor device (Col. 8, Lines 43-44. "...the two active devices in the NTP."), a first signal is input to the first semiconductor device (Col. 2, Lines 40-43, "The method includes receiving a first input signal at the inverting input, wherein the first device alters magnitude of the current passing through the first device in response to the first input signal…"), a first amplifier circuit includes the first semiconductor device (Col. 1, Lines 41-42, "...a differential amplifier circuit includes a first device…"), and a differential amplifier unit is electrically connected to the first semiconductor device (Col. 1, Lines 41-42, "...a differential amplifier circuit includes a first device…").
However, as previously combined, they do not teach and a current mirror unit is electrically connected to the differential amplifier unit.
However, in the same field of endeavor, Moue teaches a current mirror unit is electrically connected to the differential amplifier unit ([0066], "The differential input unit 21, the current mirror unit 22, and the tail current source 23 constitute a differential amplifier 20.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the OP-AMP as described by the combination of Brown, Wang, and Sugimoto with the mirror unit of Moue for "reducing power consumption", (Noue, [0005]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 6781459 B1), in view of Wang (US 20220180809 A1), Sugimoto (US 20200177143 A1), Moue (US 20220046197 A1), and Kim (US 20190312553 A1).
Regarding dependent claim 9, Brown, as previously modified by Wang, Sugimoto, and Moue, teaches the OP-AMP according to claim 8, and further teaches wherein the plurality of the semiconductor devices includes a second semiconductor device (Col. 1, Lines 41-42, "...a differential amplifier circuit includes a first device…", Col. 1, Line 48, "…a second device…"), the first signal is input to the second semiconductor device (Col. 1, Lines 53-55, "...the second device alters magnitude of current that flows through the fifth terminal in response to a signal applied to the fourth terminal…"), and the second semiconductor device is different from the first semiconductor device (Col. 2, Lines 56-60, "The first device is of a first conductivity type, has a first terminal coupled to an input, has a second terminal coupled to a first output and coupled to a first potential, and has a third terminal; the second device is of a second conductivity type that is complementary to the first conductivity type...").
However, as previously combined, they do not teach and a second amplifier circuit is electrically connected to the first amplifier circuit and includes the second semiconductor device and a source ground amplifier unit electrically connected to the second semiconductor device.
However, in the same field of endeavor, Kim teaches and a second amplifier circuit is electrically connected to the first amplifier circuit (Fig. 9A, 710, 720; [0084], "Referring to FIG. 9A, an amplification block 700 includes a first amplifier circuit 710 and a second amplifier circuit 720.") and includes the second semiconductor device and a source ground amplifier unit electrically connected to the second semiconductor device (Fig. 8A, 611, 612; [0077], "That is, the first transistor 611 and the second transistor 612 are connected in series, the first transistor 611 may operate as a common source amplifier as an input terminal, and the second transistor 612 may operate as a common gate amplifier as an output terminal...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the OP-AMP as described by the combination of Brown, Wang, Sugimoto, and Moue with the second amplifier circuit of Kim so that "the amplifier AMP may operate as a cascode amplifier", (Kim, [0077]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown (US 6781459 B1), in view of Wang (US 20220180809 A1), Sugimoto (US 20200177143 A1), Moue (US 20220046197 A1), Kim (US 20190312553 A1), and Kim (US 20220206638 A1, hereinafter Kim2).
Regarding dependent claim 10, Brown, as previously modified by Wang, Sugimoto, Moue, and Kim, teaches the OP-AMP according to claim 9. However, as previously combined, they do not teach a display device comprising a plurality of pixels electrically connected to the OP-AMP.
However, in the same field of endeavor, Kim2 teaches a display device ([0261], "In the touch display device 100…") comprising a plurality of pixels electrically connected to the OP-AMP (Fig. 12, OP-AMP, TL; [0275], "The preamplifier Pre-AMP may include an operational amplifier OP-AMP including a first input terminal IN1 to which a touch driving signal TDS is input, a second input terminal IN2 electrically connected to a touch line TL…", [0263], "Meanwhile, a first touch line TL1 may be disposed to overlap the area in which the first sub-pixel SP1 is disposed...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the OP-AMP as described by the combination of Brown, Wang, Sugimoto, Moue, and Kim with the display device of Kim2 so as to "perform load-free driving capable of reducing parasitic capacitance" (Kim2, [0281]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20020101269 A1, pertaining to an operational amplifier.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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