DETAILED ACTION
This action is in response to the application filed on 23 July 2024.
Claims 1-18 are under examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 10-15 rejected under 35 U.S.C. § 103 as being unpatentable over Herrmann et al. (US 2019/0057051 A1) in view of Takashige et al. (US 2008/0298274 A1), and further in view of Cai et al. (US 2010/0323666 A1).
Claim 1 recites “1. A system comprising: multiple destination components; and interface circuitry including a set of virtual channel ports, and a table mapping each of the virtual channel ports, of the set of virtual channel ports, to at least one of the multiple destination components, the interface circuitry configured to: receive an update packet via a first virtual channel port of the set of virtual channel ports, in which the first virtual channel port is associated with a first destination component of the multiple destination components in a current version of the table: wherein the first destination component is configured to: receive the update packet from the interface circuitry, and parse the update packet to determine that, in the current version of the table, a first value of the update packet maps to a particular destination component, of the multiple destination components, that is associated with a particular virtual channel port, of the set of virtual channel ports, and a second value of the update packet represents a new destination component, of the multiple destination components, to be associated with the particular virtual channel port; and cause the interface circuitry to modify the current version of the table to generate an updated version of the table in which the second value is written in place of the first value to associate the particular virtual channel port with the new destination component, such that the system is configured to route a subsequent packet received via the particular virtual channel port to the new destination component associated with the second value of the update packet.”
Herrmann teaches “A system comprising: multiple destination components; and interface circuitry including a set of virtual channel ports”. In particular, Herrmann discloses a MIPI CSI-2 video device having a host processor 210 including input video port(s) 306 that receive data over a plurality of virtual channels and a virtual-channel data decoder 320 that decodes data received on the virtual channels (Herrmann ¶¶3-4, 36-37). Herrmann further teaches multiple downstream destination components for the received virtual-channel data, including memory 330 and multiple image signal processors 360, 362, with the image signal processors expressly being allocated on a per-virtual-channel basis (Herrmann ¶¶42-45). Herrmann further explains that the host-processor circuitry may comprise a series of input ports for the supported virtual channels and that the system is applicable to dynamically programmable devices receiving multiple selectable/actionable virtual channels (Herrmann ¶¶67, 69).
Herrmann further teaches programmability associated with the virtual channels. The host processor configures software-configurable registers, selects which virtual channels are enabled, selects a virtual channel to operate as a master channel, and controls capture and processing of data received over the different virtual channels (Herrmann ¶¶38-41, 47-55). Thus, Herrmann establishes the claimed general architecture of virtual-channel interface circuitry coupled to multiple downstream components.
However, Herrmann does not expressly teach “a table mapping each of the virtual channel ports, of the set of virtual channel ports, to at least one of the multiple destination components” or the claimed packet-driven modification of such a mapping so that subsequent packets on a particular virtual channel are routed according to an updated association.
Takashige teaches the missing dynamically updateable virtual-channel mapping mechanism. Takashige expressly teaches a virtual channel table 16 and a physical channel table 17 maintained by a virtual network facility 13 (Takashige ¶¶33-48). The virtual channel table stores correspondences involving virtual channels, while the physical channel table stores correspondences between virtual channels and physical channels/interfaces. Takashige further expressly recognizes the conventional concept of mapping a virtual channel to a physical device identified by an address and thereafter transmitting packets according to that mapping (Takashige ¶¶10-16, 41-48, 65-90).
Takashige further teaches the claimed concept of “receive an update packet” and having a downstream processing component receive and process that packet. Specifically, Takashige's virtual NIC processor 131 receives packets and distinguishes administrative packets from ordinary data packets; an administrative packet is passed to administrative packet processor 133, which processes the contents of the packet and updates the virtual channel and/or physical channel tables according to those contents (Takashige ¶¶44-48, 116-120, 131-142).
More particularly, Takashige teaches an “allocated channel ID update processing” operation. After a virtual channel is allocated to a physical channel, administrative packet processor 133 transmits a virtual channel allocation notification packet 805 to the other computer. The packet includes a source physical network address, destination physical network address, packet identifier, and the virtual-channel ID to be allocated, and its packet identifier expressly indicates “ID update” (Takashige ¶¶221-227).
At the receiving side, virtual NIC processor 131 receives the virtual channel allocation notification packet and provides it to administrative packet processor 133. Administrative packet processor 133 then refers to physical channel table 17, uses address information contained in the received update packet to select the appropriate existing physical-channel record, and updates the channel-ID field of the selected table record to the virtual-channel ID contained in the received update packet (Takashige ¶¶228-229). Thus, Takashige teaches using information carried by an update packet to identify an existing mapped table entry and to modify that entry with mapping information carried by the update packet.
Takashige additionally teaches the consequence recited by “such that the system is configured to route a subsequent packet received via the particular virtual channel port to the new destination component.” Takashige explains that after virtual channel A is allocated to physical channel [a], a subsequently received packet belonging to physical channel [a] is controlled according to the resulting virtual-channel association (Takashige ¶¶219-224). Takashige further expressly explains that the system waits for confirmation that the receiving-side physical-channel table has been updated before transmitting subsequent data because otherwise the subsequent packet might be mistranslated by reference to the incorrect prior information in the table (Takashige ¶¶230-233). This establishes that subsequent packet handling depends upon the updated table mapping.
Takashige also teaches that the channel-allocation information need not be carried in a separate administrative packet: the virtual-channel allocation packet may be included within a data packet, with virtual-channel identification information carried in a VLAN tag, and the receiving circuitry may generate the update operation based upon the contents of that received packet (Takashige ¶¶234-238).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Herrmann's programmable multi-virtual-channel interface architecture to employ Takashige's table-based virtual-channel mapping and packet-driven mapping-update mechanism. Both references concern processing data received over virtual channels and determining how such virtual-channel data is directed to available processing/storage resources. Takashige expressly teaches that stored channel correspondences permit channel assignments to be dynamically allocated and reallocated and that later packets are processed using the updated correspondence. Applying that known mechanism to Herrmann would predictably permit the destination associated with one of Herrmann's virtual channels to be changed dynamically while allowing later packets received over that virtual channel to be directed according to the current mapping, thereby providing flexible runtime configuration of Herrmann's multi-channel processing architecture.
Herrmann as modified by Takashige, however, does not expressly disclose the particular implementation recited by “parse the update packet to determine that, in the current version of the table, a first value of the update packet maps to a particular destination component ... and a second value of the update packet represents a new destination component ... to be associated with the particular virtual channel port” and “modify the current version of the table to generate an updated version of the table in which the second value is written in place of the first value.” Although Takashige teaches selecting an existing mapped table record using information contained in an update packet and changing the selected record using further information contained in that packet, Takashige does not expressly characterize the packet contents in the claimed first-value/second-value manner.
Cai teaches this remaining message-driven table-update implementation. Cai discloses table 300 having destination identifiers mapped to stored values (“message indicators”) (Cai ¶36, Fig. 3). Cai further teaches generating and transmitting an update message that includes information identifying the destination whose mapped information is to be changed (Cai ¶¶41, 43). Upon receipt of the update message, the central database searches table 300 using the destination identifier contained in the update message, determines the value mapped to that destination, and updates the mapped value based upon the information contained in the update message. Cai expressly provides examples in which an existing value of “0” is replaced by “1,” and, upon receipt of a later update message, an existing value of “1” is replaced by “0” (Cai ¶¶42, 44; Fig. 7). Thus, Cai teaches the known implementation technique of using information in an update message to identify an existing table mapping and additional information represented by the update message to replace/update the value associated with the identified mapping.
It would have been obvious to one of ordinary skill in the art to implement the Herrmann-Takashige packet-driven virtual-channel mapping update using Cai's known update-message/table-update technique, such that the update packet provides information identifying the presently mapped association and information specifying the replacement association, with the replacement information written into the corresponding mapped entry. Cai teaches that such an arrangement permits a receiving component to determine from an update message which existing mapped entry is affected and to update that entry directly from information conveyed by the update message. Applying that conventional update technique to Takashige's dynamically reconfigurable channel-routing table would have been a predictable use of a known technique to update analogous stored mapping information, resulting in the claimed first value identifying the current destination association, the second value identifying the replacement destination, replacement of the current association with the new association, and subsequent routing according to the updated mapping.
Accordingly, claim 1 would have been obvious over Herrmann in view of Takashige and Cai.
Regarding claim 2, Herrmann further teaches “The system of claim 1, wherein the interface circuitry includes an interconnect coupled to the multiple destination components and an interface coupled to the interconnect and containing the set of virtual channel ports.” Herrmann discloses host processor 210 having input video port(s) 306 receiving data over multiple virtual channels and a virtual-channel data decoder 320, with decoded data being transferred to memory 330 and subsequently to image signal processors 360, 362 (Herrmann ¶¶36–37, 42–45). Thus, Herrmann teaches interface circuitry containing the virtual-channel ports and interconnected with multiple downstream destination components.
Regarding claim 3, Herrmann further teaches “The system of claim 2, wherein the interface is a camera serial interface 2 (CSI-2) data interface that is configured to receive different types of data at the set of virtual channel ports.” Herrmann expressly discloses a MIPI CSI-2 interface supporting concurrent reception from multiple virtual channels and teaches that the received signals comprise both video data and embedded data, with embedded data being non-image data processed differently from the video stream (Herrmann ¶¶3–5, 22, 36–37).
Regarding claim 4, Takashige further teaches “The system of claim 1, wherein the first destination component is a data modification module (DMM).” Takashige discloses administrative packet processor 133 within virtual network facility 13, wherein the administrative packet processor receives administrative packets and updates virtual channel table 16 and physical channel table 17 according to the contents of the administrative packets (Takashige ¶¶33–36, 44–48). More particularly, upon receipt of a virtual-channel allocation notification packet, administrative packet processor 133 processes the packet and updates the corresponding channel ID in physical channel table 17 (Takashige ¶¶226–229). Thus, administrative packet processor 133 constitutes a data modification module as broadly claimed.
Regarding claim 5, Herrmann further teaches “The system of claim 4, wherein the new destination component is a data register.” Herrmann discloses a set of status registers 380 managed by virtual channel data decoder 320 and further discloses software-configurable registers in memory 330 (Herrmann ¶¶25–26, 38, 40). The status registers store information concerning current operating conditions and data locations, while the software-configurable registers are configured and modified by the host processor (Herrmann ¶¶38, 40). Thus, Herrmann teaches a data register as a destination component.
Regarding claim 6, Takashige further teaches “The system of claim 1, wherein the interface circuitry is further configured to route, using one of the current version of the table and the updated version of the table, a packet received via a second virtual channel port, of the set of virtual channel ports, to a component, of the multiple components, mapped to the second virtual channel port.” Takashige teaches that virtual channel table 16 and physical channel table 17 store correspondences between virtual channels and network interfaces/channels and that virtual NIC processor 131 refers to those tables to identify the physical channel associated with a virtual channel for packet transfer (Takashige ¶¶41–48). Takashige further teaches updating the physical-channel table based on an administrative packet and subsequently processing packets according to the updated association (Takashige ¶¶219–233).
Regarding claim 7, Takashige further teaches “The system of claim 6, wherein the packet is received and routed before the update packet is received.” Takashige teaches packet transmission according to existing virtual-channel/physical-channel mappings and subsequently changing those mappings through administrative packet processing (Takashige ¶¶41–48, 219–229). Takashige further explains that, during the update process, transmission is stopped until confirmation that the receiving-side physical-channel table has been updated because otherwise a packet could be processed using the prior table information (Takashige ¶¶230–233). Thus, packets are ordinarily received and routed according to the pre-update mapping before receipt and processing of the update packet.
Regarding claim 8, Herrmann further teaches “The system of claim 6, wherein the packet is data captured by a sensor configured to be coupled to the interface circuitry.” Herrmann teaches a vehicle camera system in which host processor 210 is coupled to a plurality of cameras 250 and receives video data and embedded data from the cameras over the virtual channels (Herrmann ¶¶31–37). The input video port(s) 306 receive the plurality of video-data signals from those camera sources, thereby teaching sensor-captured data supplied to the interface circuitry.
Regarding claim 10, Herrmann further teaches “The system of claim 1, wherein the system is configured to be coupled to an external memory.” Herrmann teaches memory 330 operably coupled to host processor 210 for receiving and storing decoded data from the virtual channels (Herrmann ¶¶22, 36–38, 42). Herrmann further identifies memory 330 as system RAM and shows the memory as a storage destination for virtual-channel data (Herrmann ¶42).
Claim 11 is rejected under 35 U.S.C. § 103 as being unpatentable over Herrmann et al. in view of Takashige et al. and Cai et al. Claim 11 recites substantially the same subject matter as claims 1 and 4 in method form, including receiving an update packet via a virtual channel port, determining the destination of the update packet according to a current mapping table, forwarding the update packet to a data modification module (DMM), parsing the update packet by the DMM to identify the current and new destination information, and modifying the table to associate the particular virtual channel port with the new destination component. Accordingly, claim 11 is rejected for substantially the same reasons set forth above with respect to claims 1 and 4.
Regarding claim 12, Takashige further teaches “The method of claim 11, further comprising: routing, based on the updated version of the table, a subsequent packet received via the particular virtual channel port to the new destination component associated with the second value of the update packet.” In particular, Takashige teaches that after virtual channel A is allocated to physical channel [a], subsequently received packets are processed according to the resulting virtual-channel/physical-channel association (Takashige ¶¶219–224). Takashige further teaches waiting for confirmation that the receiving-side physical-channel table has been updated before transmitting subsequent data, because otherwise the subsequent packet may be translated using the incorrect prior information in the table (Takashige ¶¶230–233). Thus, subsequent packet routing is performed according to the updated channel mapping.
Regarding claim 13, Herrmann further teaches “The method of claim 11, further comprising: identifying different types of data using the set of virtual channel ports.” Herrmann teaches that MIPI CSI-2 permits concurrent reception over multiple virtual channels, wherein the virtual channels signify different data sources (Herrmann ¶3), and further teaches receiving video data and embedded data over the virtual channels and segregating the video data from the embedded data for different processing (Herrmann ¶¶18, 22, 30, 37–40).
Regarding claim 14, Herrmann further teaches “The method of claim 11, wherein the receiving, determining and forwarding steps are performed by a camera serial interface 2 (CSI-2) data interface, which contains the set of virtual channel ports.” Herrmann expressly teaches a video device supporting the MIPI CSI-2 standard, wherein camera input provides a set of virtual-channel signals to host processor 210 and input video ports 306 receive data from the plurality of virtual channels (Herrmann ¶¶3–4, 36–37; Fig. 3). Herrmann further teaches that virtual-channel data decoder 320 decodes the data received on the respective virtual channels and forwards the decoded data for downstream storage/processing (Herrmann ¶37).
Regarding claim 15, Herrmann further teaches “The method of claim 14, further comprising: routing, using one of the current version of the table and the updated version of the table, a first packet received via a second virtual channel port, of the set of virtual channel ports, to a memory, of the multiple destination components, mapped to the second virtual channel port; and routing, using the one of the current version of the table and the updated version of the table, a second packet received via a third virtual channel port, of the set of virtual channel ports, to a register, of the multiple destination components, mapped to the third virtual channel port.”
Herrmann teaches receiving data over multiple virtual channels and routing decoded data from selected virtual channels to memory 330 (Herrmann ¶¶36–42). Herrmann specifically teaches that data from a first virtual channel VC0 is stored in one section of memory 330 and data from another selected virtual channel VCm is stored in a different section of memory 330 (Herrmann ¶42). Herrmann additionally teaches software-configurable registers and status registers associated with processing the received virtual-channel data (Herrmann ¶¶38, 40). Takashige teaches determining the destination of packets according to stored virtual-channel mappings and processing subsequent packets according to the updated mapping (Takashige ¶¶41–48, 219–224, 230–233). Accordingly, it would have been obvious to use Takashige's table-based routing mechanism with Herrmann's multiple virtual-channel destinations so that data received through different virtual channels is directed to the respective mapped memory/register destinations.
Claims 9 and 18 are rejected under 35 U.S.C. § 103 as being unpatentable over Herrmann et al. in view of Takashige et al. and Cai et al., and further in view of Dodrill et al. (US 6, 697,964).
Regarding claim 9, the combination of Herrmann, Takashige, and Cai does not expressly teach “The system of claim 2, wherein the interface is configured to be coupled to a playback component for testing of the system.”
Dodrill teaches a load-generation/testing system configured to test an application server by executing prescribed scripts representing sequences of requests that ordinarily would be supplied during actual operation. The load generator generates repeatable simulated input to the system under test, thereby permitting testing of system operation under predetermined input sequences (Dodrill, Abstract; 5:45-6:7, 6:37+, see also the description of load generation system 16 and prescribed scripts).
It would have been obvious to one of ordinary skill in the art to configure the interface of the modified Herrmann system to be coupled to a playback/load-generation component as taught by Dodrill so as to provide predetermined input data to the interface for testing, thereby permitting repeatable testing of the operation of the multi-channel interface and its downstream processing components.
Regarding claim 18, Herrmann in view of Takashige and Cai teaches the method of claim 15 as discussed above, but does not expressly teach “The method of claim 15, further comprising: performing a test on a system implementing at least a part of the method based on data of the first packet and data of the second packet.”
Dodrill teaches performing testing on a system using test data, including a test system/load generator that supplies data to exercise a system under test and evaluate its operation. (Dodrill, Abstract; 5:45-6:7, 6:37+).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the testing technique of Dodrill to the system implementing the method of Herrmann as modified by Takashige and Cai, using the first- and second-packet data already present in that system, in order to test and verify proper operation of the system.
Claims 16 and 17 are rejected under 35 U.S.C. § 103 as being unpatentable over Herrmann et al. in view of Takashige et al. and Cai et al., and further in view of Hwang.(US Pub. 2022/0086609).
Regarding claim 16, Herrmann in view of Takashige and Cai teaches the method of claim 15 as discussed above, but does not expressly teach “The method of claim 15, further comprising: altering an operation of a driver assist system in a vehicle based on at least one of data of the first packet stored in the memory and data of the second packet stored in the register.” Hwang teaches an ADAS vehicle having sensors for driver driving assistance, wherein sensor data are collected, fused, and provided to an ADAS application (Hwang ¶86). It would have been obvious to one of ordinary skill in the art to use the sensor data processed by the modified Herrmann system in an ADAS application as taught by Hwang in order to provide driver assistance based on the sensor data.
Regarding claim 17, Hwang further teaches “The method of claim 16, wherein the data of the first packet includes radar sensor data and the data of the second packet includes image data.” Hwang expressly teaches that sensors mounted on an ADAS vehicle include a camera and a radar and that data from such sensors are collected, fused, and provided to an ADAS application (Hwang ¶86). It would have been obvious to one of ordinary skill in the art to employ Hwang's radar sensor data and camera image data as the respective sensor data processed by the modified Herrmann system because Hwang teaches using these known complementary sensor data in an ADAS vehicle for driver assistance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure (see form 892).
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/Luat Phung/
Primary Examiner, Art Unit 2468
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