DETAILED ACTION
This office action is responsive to application 18/780,883 filed on July 23, 2024. Claim 1 is pending in the application and has been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS) filed on August 19, 2024 and January 21, 2025 were received and have been considered by the Examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 14/851,785, filed on September 11, 2015.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Olsen et al. (US 2008/0029714) in view of Kinsman et al. (US 2013/0221470).
Consider claim 1, Olsen et al. teaches:
An imaging element comprising a plurality of semiconductor substrates (Olsen et al. details “in some embodiments one, some or all portions of the processor are disposed on one or more substrates that are separate from (and possibly remote from) one or more substrates on which one or more of the one or more sensor arrays, e.g., sensor arrays 310A-310D, may be disposed” paragraph 0805. The substrates are semiconductor substrates, paragraphs 0089, 0327, 0330, 0343, 0375 and 0377.), wherein
the plurality of semiconductor substrates include
a plurality of photoelectric converting sections (sensor arrays 310A-310D, figure 8, paragraph 0385) that convert light into charges (see paragraph 0392),
a first computational circuit that performs a computational process using a signal based on a charge converted by a first photoelectric converting section among the plurality of photoelectric converting sections, a second computational circuit that performs a computational process using a signal based on a charge converted by a second photoelectric converting section among the plurality of photoelectric converting sections (The sensor arrays (310A-310D) are connected to a processor (340), figure 8, paragraph 0389. The processor (340) includes a plurality of channel processors (i.e. computational circuits) which are respectively connected to the sensor arrays of the respective camera channels, paragraph 0807, figure 110A). The respective channel processors (i.e. computational circuits) perform computational processes through analog signal logic, black level logic, and exposure control, figure 110B, paragraphs 0810-0813.), and
a drive control section (“system control”, figures 110A and 110E, paragraph 0817) that performs a control such that the computational process performed in the first computational circuit is different from the computational process performed in the second computational circuit (Each channel processor is tailored to its associated camera channel such that different computational processes are performed for different wavelengths or colors of the respective camera channels, paragraphs 0807, 0808 and 0810-0813.).
However, Olsen et al. does not explicitly teach that the plurality of semiconductor substrates are stacked on each other.
Kinsman et al. similarly teaches an imaging element comprising a plurality of photoelectric converting sections (pixel arrays (20) of image sensor chip (16), figure 2, paragraphs 0019 and 0020) included in a first substrate (integrated circuit substrate, 17, paragraph 0019) and image processing circuitry (control and processing circuitry, 18, paragraph 0016) included in a second substrate (“image signal processing die”, paragraph 0024, figure 3).
However, Kinsman et al. additionally teaches that the first and second substrates are stacked (see 16 and 18 of figure 3, paragraph 0024).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of the invention to have the plurality of semiconductor substrates taught by Olsen et al. be stacked on each other as taught by Kinsman et al. for the benefit of providing more efficient use of area, allowing each substrate to be implemented using the most appropriate technology process, increasing the performance of die-to-die interface and simplifying printed circuit board design (Kinsman et al., paragraph 0023).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,081,882. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 is anticipated by claim 1 of US 12,081,882 as follows:
Consider claim 1, claim 1 of US 12,081,882 teaches (in parentheses):
An imaging element comprising (An imaging element comprising)
a plurality of semiconductor substrates stacked on each other (a plurality of semiconductor substrates stacked on each other), wherein
the plurality of semiconductor substrates include a plurality of photoelectric converting sections that convert light into charges (the plurality of semiconductor substrates include a first photoelectric converting section that converts light into charges, a second photoelectric converting section that converts light into charges),
a first computational circuit that performs a computational process using a signal based on a charge converted by a first photoelectric converting section among the plurality of photoelectric converting sections, (a first computational circuit that performs a computational process using a first signal based on a charge converted by the first photoelectric converting section)
a second computational circuit that performs a computational process using a signal based on a charge converted by a second photoelectric converting section among the plurality of photoelectric converting sections, (a second computational circuit that performs a computational process using a second signal based on a charge converted by the second photoelectric converting section) and
a drive control section that performs a control such that the computational process performed in the first computational circuit is different from the computational process performed in the second computational circuit (a drive control section that performs a control such that (i) the computational process performed in the first computational circuit is different from the computational process performed in at least one of the second computational circuit and the third computational circuit).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637