DETAILED ACTION
This office action is responsive to communication filed on April 24, 2026.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claims 1, 9, 10 and 14 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Tsukimura et al. (US 2013/0181316).
Consider claim 1, Tsukimura et al. teaches:
An imaging element (see figures 2, 3A, 3B and 4) comprising:
a first semiconductor section (first substrate, 20, paragraph 0097) that includes a pixel section in which a plurality of pixels are arranged in a row direction and a column direction (Pixels (1) are arranged in a two-dimensional matrix, figure 2, paragraph 0093. The pixels (1) “are distributed and arranged in the first substrate 20”, paragraph 0102.), each of the plurality of pixels (1, see figure 4) including a photoelectric converting section (photoelectric conversion element, 101, paragraph 0103) that converts light into a charge and a transfer section (transfer transistor, 102, paragraph 0103) that transfers the charge converted by the photoelectric converting section (As detailed in paragraph 0103, figure 4 shows two pixels. Each pixel includes a photoelectric conversion element (101a or 101b) and a transfer transistor (102a or 102b).);
a second semiconductor section (second substrate, 21, paragraph 0097) that includes a control section (vertical scanning section, 3, figure 2) that performs control such that a timing at which a first transfer control signal (ΦTX1) for controlling the transfer section (102a) of a first pixel among the plurality of pixels is output is different from a timing at which a second transfer control signal (ΦTX2) for controlling the transfer section (102b) of a second pixel among the plurality of pixels is output (The control signals (ΦTX1, ΦTX1) are performed at different timings, as shown in figure 7 and detailed in paragraphs 0143, 0146 and 0118. The control section (3, paragraph 0095) may be arranged in the second substrate (21), paragraph 0102.), the second pixel being arranged side by side with the first pixel in the row direction (The Examiner interprets the direction of the two pixels in figure 4 to be the row direction.), the second semiconductor section (21) being stacked with the first semiconductor section (20, see figure 3A, paragraph 0097);
a wiring layer that includes a first transfer control wiring to which the first transfer control signal is output and a second transfer control wiring to which the second transfer control signal is output, the wiring layer being arranged between the first semiconductor section and the second semiconductor section in a stack direction in which the first semiconductor section and the second semiconductor section are stacked (As shown in figure 3A, there is a wiring layer between the substrates (20, 21). The vertical scanning circuit (3) controls each pixel via a control signal line (8), paragraphs 0095, 0105, 0106 and 0118, figure 2. Supply voltages for driving the circuit elements arranged in the first substrate (20) are provided from the second substrate (21) via transfer control wirings comprising micropads (25), microbumps (27) and micropads (26), paragraph 0100, figure 3A.);
a first connection section for electrically connecting the first semiconductor section (20) and the second semiconductor section (21) and that includes first conductive members arranged to face each other in the stack direction (A first connection section (25, 26, 27) including first conductive members (25, 26) facing each other is formed as shown in figure 3A, paragraph 0100.); and
a second connection section for electrically connecting the first semiconductor section (20) and the second semiconductor section (21) and that includes second conductive members (25, 26) arranged to face each other in the stack direction (There are multiple connection sections (25, 26, 27) including conductive members (25, 26), as shown in figure 3A and detailed in paragraph 0100.), wherein
the first conductive members (25, 26) and the second conductive members (25, 26) are arranged between the pixel section and the second semiconductor section in the stack direction (i.e. due to the pixel section being formed in the first substrate (20) and the second semiconductor section (21) being the second substrate (21), see figure 3A).
Consider claim 9, and as applied to claim 1 above, Tsukimura et al. further teaches that the wiring layer (see figure 3A) includes a first output wiring (22, 23, 24) to which a first signal read from the first pixel is output and a second output wiring (22, 23, 24) to which a second signal read from the second pixel is output (Signals output from the pixels are respectively output via connectors each comprising a micropad (22), microbump (24) and micropad (23), paragraphs 0098 and 0099.).
Consider claim 10, and as applied to claim 9 above, Tsukimura et al. further teaches that the first semiconductor section (20) includes a first current source circuit section for supplying current to the first output wiring and a second current source circuit section for supplying current to the second output wiring (Each pixel pair (see figure 4) includes a current source circuit (current source, 106, paragraph 0103). Therefore, a first current source (106) is provided for a first pixel pair and a second current source (106) is provided for a second pixel pair of the pixel matrix. As detailed in paragraph 0102, the pixel circuitry is arranged in the first substrate (20).).
Consider claim 14, Tsukimura et al. teaches:
An imaging apparatus (figure 1) comprising:
the imaging element according to Claim 1 (imaging unit, 202, paragraphs 0087 and 0092, see claim 1 rationale).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 4 and 5 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tsukimura et al. (US 2013/0181316) in view of Egawa et al. (US 2005/0162537).
Consider claim 2, and as applied to claim 1 above, Tsukimura et al. teaches a discharge section (FD reset transistor, 104, paragraph 0103). Tsukimura et al. teaches that a discharge section (104) is shared by two pixels (see figure 4).
As such, Tsukimura et al. does not explicitly teach that the plurality of pixels each include a discharge section that discharges the charge converted by the photoelectric converting section, wherein the control section performs control such that a timing at which a first discharge control signal for controlling the discharge section of the first pixel is output is different from a timing at which a second discharge control signal for controlling the discharge section of the second pixel is output, in combination with the other elements recited in parent claim 1.
Egawa et al. similarly teaches an imaging element (figure 12) with a plurality of pixels (cells, 1, paragraph 0049) and a discharge section (transistor Tc, paragraph 0049).
However, Egawa et al. additionally teaches that the plurality of pixels (1) each include a discharge section (Tc, see figure 12) that discharges the charge converted by a photoelectric converting section (i.e. according to ΦRESET, paragraph 0053), wherein a control section (timing generation circuit, 8, figure 12) performs control such that a timing at which a first discharge control signal (ΦRESET1) for controlling the discharge section of the first pixel is output is different from a timing at which a second discharge control signal (ΦRESET2) for controlling the discharge section of the second pixel is output (see figure 14, paragraph 0089).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of the invention to provide independently operated discharge sections as taught by Egawa et al. for each of the plurality of pixels taught by Tsukima et al. for the benefit that the number of lines per horizontal effective scanning period can be increased (Egawa et al., paragraph 0093).
Consider claim 4, and as applied to claim 2 above, Tsukimura et al. further teaches that the wiring layer (see figure 3A) includes a first output wiring (22, 23, 24) to which a first signal read from the first pixel is output and a second output wiring (22, 23, 24) to which a second signal read from the second pixel is output (Signals output from the pixels are respectively output via connectors each comprising a micropad (22), microbump (24) and micropad (23), paragraphs 0098 and 0099.).
Consider claim 5, and as applied to claim 4 above, Tsukimura et al. further teaches that the first semiconductor section (20) includes a first current source circuit section for supplying current to the first output wiring and a second current source circuit section for supplying current to the second output wiring (Each pixel pair (see figure 4) includes a current source circuit (current source, 106, paragraph 0103). Therefore, a first current source (106) is provided for a first pixel pair and a second current source (106) is provided for a second pixel pair of the pixel matrix. As detailed in paragraph 0102, the pixel circuitry is arranged in the first substrate (20).).
Allowable Subject Matter
Claims 3, 6-8 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 3, the prior art of record does not teach nor reasonably suggest that the wiring layer includes a first discharge control wiring to which the first discharge control signal is output and a second discharge control wiring to which the second discharge control signal is output, in combination with the other elements recited in parent claims 1 and 2.
Consider claim 6, Tsukimura et al. teaches peripheral circuits including ADC circuits (601A, 601B, figure 13, paragraph 0192).
However, the prior art of record does not explicitly teach that the second semiconductor section includes a first convert section for converting the first signal outputted to the first output wiring into a first digital signal and a second convert section for converting the second signal outputted to the second output wiring into a second digital signal, in combination with the other elements recited in parent claims 1, 2, 4 and 5.
Claims 7 and 8 contain allowable subject matter as depending from claim 6.
Consider claim 11, Tsukimura et al. teaches peripheral circuits including ADC circuits (601A, 601B, figure 13, paragraph 0192).
However, the prior art of record does not explicitly teach that the second semiconductor section includes a first convert section for converting the first signal outputted to the first output wiring into a first digital signal and a second convert section for converting the second signal outputted to the second output wiring into a second digital signal, in combination with the other elements recited in parent claims 1, 9 and 10.
Claims 12 and 13 contain allowable subject matter as depending from claim 11.
Double Patenting
All double patenting rejections are hereby removed in view of Applicant’s response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Solhusvik et al. (US 2013/0068929) teaches a vertically stacked imager (figure 3) with a pixel array on an upper layer (17) and control circuitry on a lower layer (44).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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