Prosecution Insights
Last updated: October 01, 2026
Application No. 18/780,907

Radio-frequency Amplifier with Multiple Power Control Loops

Non-Final OA §103
Filed
Jul 23, 2024
Examiner
SHAMIRYAN, NAREH
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
54 granted / 60 resolved
+22.0% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
17 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
38.5%
-1.5% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
31.3%
-8.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 60 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Foreign priority is not claimed for this application. Information Disclosure Statement The information disclosure statements (IDS) submitted on 07/23/2024 and 12/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Objections Claim 1 is objected to because of the following informalities: Line 3 should read “a power detection circuit coupled to an output of the one or more transmit circuits.” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9954564 by Little et al. Regarding claim 1, Little teaches wireless circuitry comprising: one or more transmit circuits operable using a plurality of different mode settings (Fig. 6a); a power detection circuit (coupler 100b) coupled to an output the one or more transmit circuits; a plurality of power integrators (filters 134; in simplest form, an RC filter is an integrator); and a first switching circuit (136a) having an input configured to receive a measured power level from the power detection circuit and having outputs coupled to the plurality of power integrators (134), wherein the first switching circuit (136a) has a switch state that is adjusted based on a current mode setting in the plurality of different mode settings for the one or more transmit circuits (Col. 10 lines 42-59). Regarding claim 2, Little teaches the wireless circuitry of claim 1, further comprising: a mode controller configured to output a control word, wherein the control word determines the current mode setting for the one or more transmit circuits (Col. 14 lines 4-29); and a switch controller (Fig. 7 #120) configured to receive the control word from the mode controller and adjust the switch state of the first switching circuit (Fig. 6a #136a). Regarding claim 3, Little teaches the wireless circuitry of claim 2, wherein the plurality of power integrators comprises: a first power integrator (Fig. 6a #134 one of the multiple filters) having an input coupled to the first switching circuit (136a) and configured to produce a first integrated power level; and a second power integrator (Fig. 6a #134) having an input coupled to the first switching circuit (136a) and configured to produce a second integrated power level. Regarding claim 8, Little teaches the wireless circuitry of claim 1, wherein: a first mode setting in the plurality of different mode settings is used when the wireless circuitry is processing signals in accordance with a first modulation scheme; and a second mode setting in the plurality of different mode settings is used when the wireless circuitry is processing signals in accordance with a second modulation scheme different than the first modulation scheme (Col. 4 lines 7-13; Col. 14 lines 25-29; the switches and filters (integrators) and other components of the circuit are controlled based on different operation modes and modulation schemes). Regarding claim 9, Little doesn’t explicitly mention different modulation schemes, however these are well known in the art and are simply a design choice for the circuit, as taught in par. 69 of US 20190312762 by Dionisi. Claim(s) 1, 10-14, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20060246858 by Boerman et al. in view of US 9954564 by Little et al. Regarding claim 1, Boerman teaches wireless circuitry comprising: one or more transmit circuits operable using a plurality of different mode settings (plurality of samplers used based on circuit needs); a power detection circuit (324) coupled to an output the one or more transmit circuits; a plurality of power integrators (samplers). Boerman mentions controlling the power amplifier using the samplers based on the detected output level (Abstract), but doesn’t teach a first switching circuit having an input configured to receive a measured power level from the power detection circuit and having outputs coupled to the plurality of power integrators. However, Little teaches wireless circuitry with a first switching circuit (Fig. 6a #136a) having an input that’s configured to receive a measured power level from the power detection circuit and having outputs coupled to the plurality of power integrators (filters #134). It would have been obvious to combine the switching circuit of Little with the detector and samplers (integrators) of Boerman in order control the power amplifier based on the power of the detected output signal. Paragraph 11 of Boerman also mentions an embodiment with a switch connected to the samplers. Regarding claim 10, the combination of Boerman and Little teaches the wireless circuitry of claim 1, wherein: a first mode setting in the plurality of different mode settings is used to bias a radio-frequency amplifier in the one or more transmit circuits with a first bias setting; and a second mode setting in the plurality of different mode settings is used to bias the radio-frequency amplifier with a second bias setting different than the first bias setting (Boerman Abstract: control signal is used to control the gain of the amplifier and it’s well known in the art that different bias settings control amplifier gain (Par. 12 of US 20110050347 by Trainor et al.)). Regarding claim 11, Boerman teaches wireless circuitry comprising: a radio-frequency amplifier (Fig. 4 #308) operable using a plurality of different bias settings (Abstract “amplifier control signal”); a power detection circuit (324) coupled to an output of the radio-frequency amplifier; a plurality of power integrators (samplers). Boerman mentions controlling the power amplifier using the samplers based on the detected output level (Abstract), but doesn’t teach a first switching circuit having an input configured to receive a measured power level from the power detection circuit and having outputs coupled to the plurality of power integrators. However, Little teaches wireless circuitry with a first switching circuit (Fig. 6a #136a) having an input that’s configured to receive a measured power level from the power detection circuit and having outputs coupled to the plurality of power integrators (filters #134). It would have been obvious to combine the switching circuit of Little with the detector and samplers (integrators) of Boerman in order control the power amplifier based on the power of the detected output signal. Paragraph 11 of Boerman also mentions an embodiment with a switch connected to the samplers. Regarding claim 12, the combination of Boerman and Little teaches the wireless circuitry of claim 11, further comprising: a bias circuit configured to output one or more bias signals to the radio-frequency amplifier based on a control word that at least partially determines the current bias setting for the radio-frequency amplifier (Boerman Par. 33-35: DSP can comprise but is not limited to, a digital signal processor, ASIC, logic, controller, processor, microprocessor, ARM, or any modulation control element. DSP can provide signals that control the gain of the amplifier (well known in the art that gain is controlled by different bias settings/signal (Par. 12 of US 20110050347 by Trainor et al.)). Regarding claim 13, the combination of Boerman and Little teaches the wireless circuitry of claim 12, further comprising: a bias controller configured to output the control word (Little Col. 14 lines 4-29); and a switch controller (Little Fig. 7 #120) configured to receive the control word from the bias controller and adjust the switch state of the first switching circuit (Little Fig. 6a #136a). Regarding claim 14, the combination of Boerman and Little teaches the wireless circuitry of claim 13, wherein the plurality of power integrators comprises: a first power integrator (Little Fig. 6a #134 one of the multiple filters; Boerman Fig. 4 samplers) having an input coupled to the first switching circuit (Little 136a) and configured to produce a first integrated power level; and a second power integrator (Little Fig. 6a #134; Boerman Fig. 4 samplers) having an input coupled to the first switching circuit (Little 136a) and configured to produce a second integrated power level. Regarding claim 18, the combination of Boerman and Little teaches the wireless circuitry of claim 11, wherein: a first bias setting in the plurality of different bias settings is used when the wireless circuitry is processing signals in accordance with a first modulation scheme; a second bias setting in the plurality of different bias settings is used when the wireless circuitry is processing signals in accordance with a second modulation scheme different than the first modulation scheme (Little Col. 4 lines 7-13; Col. 14 lines 25-29; the switches and filters (integrators) and other components of the circuit are controlled based on different operation modes and modulation schemes; Boerman par. 33: DSP 304 can be used for modulation control); the first modulation scheme comprises quadrature phase shift keying (QPSK); and the second modulation scheme comprises 64-quadature amplitude modulation (64-QAM), 128-quadrature amplitude modulation (128-QAM), 256-quadrature amplitude modulation (256-QAM), 512-quadrature amplitude modulation (512-QAM), or 1024-quadrature amplitude modulation (1024-QAM) (different modulation schemes are well known in the art and are simply a design choice for the circuit, as taught in par. 69 of US 20190312762 by Dionisi). Regarding claim 19, the combination of Boerman and Little teaches the wireless circuitry of claim 11, wherein: a first bias setting in the plurality of different bias settings is used when the wireless circuitry is processing signals within a first range of power levels; and a second bias setting in the plurality of different bias settings is used when the wireless circuitry is processing signals within a second range of power levels different than the first range of power levels. (Boerman Abstract: control signal is used to control the gain of the amplifier and it’s well known in the art that different bias settings control amplifier gain (Par. 12 of US 20110050347 by Trainor et al.)). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20060246858 by Boerman et al. Regarding claim 20, Boerman teaches circuitry comprising: a signal path having one or more amplifier stages (Fig. 4); a gain control circuit configured to attenuate or amplify signals along the signal path (#304, par. 35); a bias controller for outputting a control word that determines a configuration setting for the one or more amplifier stages (Par. 33-35: DSP can comprise but is not limited to, a digital signal processor, ASIC, logic, controller, processor, microprocessor, ARM, or any modulation control element. DSP can provide signals that control the gain of the amplifier (well known in the art that different bias settings control gain (Par. 12 of US 20110050347 by Trainor et al.)); and a plurality of power control loops (Fig. 4 the plurality of samplers), wherein a selected power control loop in the plurality of power control loops is activated based at least partly on the control word to provide a power correction signal to the one or more amplifier stages (Abstract: the samplers and switches control the gain of the amplifier based on the detected output signal). Allowable Subject Matter Claims 4-7 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art fails to teach a first comparator having a first input configured to receive the first integrated power level from the first power integrator; and a second comparator having a first input configured to receive the second integrated power level from the second power integrator. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20260163525 by Carvalho et al. teaches a bias circuit that outputs signals based on a control word. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NAREH SHAMIRYAN/Examiner, Art Unit 2843 /ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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Prosecution Timeline

Jul 23, 2024
Application Filed
Sep 15, 2026
Applicant Interview (Telephonic)
Sep 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+13.3%)
3y 2m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 60 resolved cases by this examiner. Grant probability derived from career allowance rate.

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