DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
131a-2 (Starting on page 5: ¶7 lines 11 and 15; ¶49 line 17; ¶50 lines 21-22; ¶52 line 6; ¶53 lines 12 and 14-16; ¶59; ¶61 line 2; ¶62 line 10; ¶63 line 13; ¶65 lines 21, 23, and 25; ¶66; ¶69; ¶79; ¶90; ¶101 lines 2 and 4; ¶102)
132a-2 (Starting on page 5: ¶7 lines 11 and 15; ¶49 line 17; ¶50 lines 21-22; ¶52 line 6; ¶53 lines 12 and 14-16; ¶59; ¶61 line 2; ¶62 line 10; ¶63 line 13; ¶65 lines 21, 23, and 25; ¶66; ¶69; ¶79; ¶90; ¶101 lines 2 and 4; ¶102)
231a-2 (¶70, ¶73)
232a-2. (¶70, ¶73)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 210, 211, 212, 221, 222, 231a, 231a-1, 231c, 231d, 232a, 232a-1, 232c, and 232d. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs are numbered correctly up to paragraph [0020], after which the paragraphs begin numbering at [0001] again, creating duplicate paragraphs numbers.
231b-1b in ¶96 is not shown in the drawings, however, from context, it is clearly a typo which should read as 231b-2. Note that 231b-2 is not shown in the drawings (see drawing objections above).
Line 7 of ¶96 recites “…231b-1 and 231b-1…” when it should recite “…231b-1 and 231b-2…”.
Note that 231b-2 is not shown in the drawings (see drawing objections above).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-12, and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2022/0165497 A1), hereafter referred to as Jeong.
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Figure 1: Examiner modified Fig. 2 of Jeong showing the band electrode layer and the connection electrode layer. Extension lines of the first surface (EL1), second surface (EL2), third surface (EL3) and fourth surface (EL4) are also depicted. The band electrode layer is chosen to be the portions of 131a and 132a above EL2 and below EL1.
Regarding claim 1, Jeong discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶28) including a dielectric layer (111 – Fig. 2 ¶28) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 2 ¶28), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface , and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape ¶28); and an external electrode (131, 132 – Fig. 2 ¶28) including an electrode layer disposed on the body and connected to the internal electrode (131a, 132a – Fig. 2 ¶28), a plating layer disposed on the electrode layer (131c1, 132c1 – Fig. 2 ¶28), and a conductive resin layer including a conductive metal and a resin (131b, 132b – Fig. 2 ¶89), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including copper (Cu) and a first glass (connection electrode layer – Figure 1 shown above ¶84-¶85), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including silver (Ag) and a second glass (band electrode layer – Figure. 1 shown above ¶84-85), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Figure 1 shown above).
Regarding claim 2, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive metal comprises copper (Cu) (¶91).
Regarding claim 3, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive metal comprises an intermetallic compound (¶98).
Regarding claim 4, Jeong discloses the multilayer electronic component of claim 1, wherein the band electrode layer is not disposed between an extension line of the first surface and an extension line of the second surface (Figure 1 shown above).
Regarding claim 6, Jeong discloses the multilayer electronic component of claim 1, wherein the band electrode layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 7, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 9, Jeong discloses the multilayer electronic component of claim 1, wherein the plating layer is not in direct contact with the band electrode layer (Figure 1 shown above; The conductive resin layer covers the entire band electrode layer).
Regarding claim 10, Jeong discloses the multilayer electronic component of claim 1, wherein the plating layer comprises a first plating layer disposed on the connection electrode layer and the conductive resin layer, and a second plating layer disposed on the first plating layer (131c1, 131c2 – Fig. 2 ¶107).
Regarding claim 11, Jeong discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶28) including a dielectric layer (111 – Fig. 2 ¶28) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 2 ¶28), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface, and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape ¶28); and an external electrode (131, 132 – Fig. 2 ¶28) including an electrode layer disposed on the body and connected to the internal electrode (131a, 132a – Fig. 2 ¶28), a plating layer disposed on the electrode layer (131c1, 132c1 – Fig. 2 ¶28), and a conductive resin layer (131b, 132b – Fig. 2 ¶89), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including a first conductive metal and a first glass (connection electrode layer – Figure 1 shown above ¶84-¶85), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including a second conductive metal and a second glass (band electrode layer – Figure. 1 shown above ¶84-85), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Figure 1 shown above), and the conductive resin layer includes a third conductive metal and a resin (¶89).
Regarding claim 12, Jeong discloses the multilayer electronic component of claim 11, wherein the band electrode layer is not disposed between an extension line of the first surface and an extension line of the second surface (Figure 1 shown above).
Regarding claim 14, Jeong discloses the multilayer electronic component of claim 11, wherein the band electrode layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 15, Jeong discloses the multilayer electronic component of claim 11, wherein the conductive resin layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 16, Jeong discloses the multilayer electronic component of claim 11, wherein the second conductive metal is softer than the first conductive metal (From ¶84-¶85, the electrode layer may include both copper and silver. The first conductive metal may then be copper and the second conductive metal may then be silver. Therefore, the second conductive metal is softer than the first conductive metal).
Regarding claim 17, Jeong discloses the multilayer electronic component of claim 11, wherein the second conductive metal and the first conductive metal are different metals (From ¶84-¶85, the electrode layer may include both copper and silver. The first conductive metal may then be copper and the second conductive metal may then be silver).
Regarding claim 18, Jeong discloses the multilayer electronic component of claim 11, wherein the resin includes an epoxy resin (¶97).
Regarding claim 19, Jeong discloses the multilayer electronic component of claim 11, wherein the second glass includes a glass frit (¶86).
Claim(s) 1, 5, 8, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2021/0065984 A1), hereafter referred to as Oh.
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Figure 2: Examiner modified Fig. 3 of Oh showing extensions lines of the first surface (EL1) and the second surface (EL2). The conductive resin layer (133, 143) is shown to only be disposed on the band electrode layer (131b, 141b) and is not disposed between EL1 and EL2.
Regarding claim 1, Oh discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶35) including a dielectric layer (111 – Fig. 3 ¶36) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 3 ¶45), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface , and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape); and an external electrode including an electrode layer disposed on the body and connected to the internal electrode (130, 140 – Fig. 1 ¶53), a plating layer disposed on the electrode layer (132, 142 – Fig. 3 ¶66), and a conductive resin layer including a conductive metal and a resin (133, 143 – Fig. 3 ¶62-¶64), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including copper (Cu) and a first glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including silver (Ag) and a second glass (131b, 141b – Fig. 3 ¶55 and ¶57-¶58), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Fig. 3).
Regarding claim 5, Oh discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is not disposed between an extension line of the first surface and an extension line of the second surface (133, 143 – Figure 2 shown above and ¶55).
Regarding claim 8, Oh discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is not in direct contact with the connection electrode layer (133, 143 – Figure 2 shown above and ¶55 discloses that the conductive resin layer is only on the band electrode layer. In other words, no portion of the conductive resin layer is shown to be disposed between the extension lines EL1 and EL2).
Regarding claim 11, Oh discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶35) including a dielectric layer (111 – Fig. 3 ¶36) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 3 ¶45), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface, and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape); and an external electrode including an electrode layer disposed on the body and connected to the internal electrode (130, 140 – Fig. 1 ¶53), a plating layer disposed on the electrode layer (132, 142 – Fig. 3 ¶66), and a conductive resin layer (133, 143 – Fig. 3 ¶62-¶64), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including a first conductive metal and a first glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including a second conductive metal and a second glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Fig. 3), and the conductive resin layer includes a third conductive metal and a resin (¶62-¶64).
Regarding claim 13, Oh discloses the multilayer electronic component of claim 11, wherein the conductive resin layer is not disposed between an extension line of the first surface and an extension line of the second surface (133, 143 – Figure 2 shown above and ¶55).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0301468 A1 – ¶10 teaches an intermetallic compound in conductive resin layer
US 2017/0154729 – Fig. 5 shows the structure in claims 5, 8, and 13 but contains no silver
US 2018/0151296 A1 – Fig. 6C shows the structure in claims 5, 8, and 13
US 2018/0174753 A1 – Fig. 2 shows a plating layer directly on connection layer
US 2022/0208474 A1 – Fig. 9 shows a structure similar to claims 5, 8, and 13
US 2013/0170095 A1 – Fig. 3 shows the structure in claims 5, 8, and 13
US 2021/0343475 A1 – ¶36 and ¶52; Fig. 5 shows the structure in claims 5, 8, and 13
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy Torres whose telephone number is (571)272-9896. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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