DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed August 26, 2026 have been fully considered but they are not persuasive.
Regarding Jeong et al. US 2022/0165497 A1 (hereafter referred to as Jeong), applicant agues
claims 1 and 11 require a connection electrode layer including copper and a first glass, a separate band electrode layer contacting the connection electrode layer and including silver and a second glass, and a conductive resin layer disposed between the band electrode layer and the plating layer, and
Jeong's general statement that an electrode layer may include one or more materials from a list that includes copper and silver does not teach or suggest the specific claimed structure in which one layer is a copper and first glass connection electrode layer and another layer is a silver and second glass band electrode layer.
In response to applicant's argument (i) that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a separate/distinct band electrode layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding argument (ii), Jeong teaches that conductive resin layers 131a and 132a may include silver and copper (paras. [0085], [0091], [0102-0103]) as Jeong explicitly discloses 131a and 131b may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. A combination which includes silver and copper is included in this teaching and therefore anticipates the limitations of claims 1 and 11.
Therefore, it is maintained that Jeong has identified every claimed feature in claims 1 and 11.
Regarding Oh et al. US 2021/0065984 A1 (hereafter referred to as Oh) applicant argues
claims 1 and 11 require a connection electrode layer including copper and a first glass, a separate band electrode layer contacting the connection electrode layer and including silver and a second glass, and a conductive resin layer disposed between the band electrode layer and the plating layer,
Oh's statement that the conductive layers may include at least one of copper and silver, and may further include glass, does not teach or suggest copper and first glass in a connection electrode layer and silver and second glass in a distinct band electrode layer contacting the connection electrode layer, and
Oh does not teach or suggest the conductive resin layer arrangement recited in the claims
In response to applicant's argument (iii) that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a separate/distinct band electrode layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding argument (iv), Oh teaches that first and second conductive layers 131 and 141 may include silver and copper (para. [0058]) as Oh explicitly discloses 131 and 141 may include at least one of copper (Cu) and silver (Ag), and may further include glass, epoxy, and the like. A combination which includes silver, copper, and glass is included in this teaching and therefore anticipates the limitations of claims 1 and 11. Furthermore, as stated above, the band electrode layer is not claimed as being separate/distinct and therefore Oh anticipates the band electrode limitation in claims 1 and 11.
Regarding argument (v), Oh explicitly teaches in para. [0062] that the impact absorbing-binder included in first and second reinforcing layers 133 and 143 may include epoxy-based or an acrylic-based binder, both of which are resins. Furthermore, 133 and 143 include metal powder and are disclosed to be conductive in para. [0065] of Oh. Therefore, 133 and 143 of Oh anticipate the claimed conductive resin layers.
The arguments following argument (v) are not persuasive as they rely on the validity of applicant’s previous arguments, which have been shown to not be persuasive.
Therefore, it is maintained that Oh has identified every claimed feature in claims 1 and 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-12, and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2022/0165497 A1), hereafter referred to as Jeong.
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Figure 1: Examiner modified Fig. 2 of Jeong showing the band electrode layer and the connection electrode layer. Extension lines of the first surface (EL1), second surface (EL2), third surface (EL3) and fourth surface (EL4) are also depicted. The band electrode layer is chosen to be the portions of 131a and 132a above EL2 and below EL1.
Regarding claim 1, Jeong discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶28) including a dielectric layer (111 – Fig. 2 ¶28) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 2 ¶28), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface , and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape ¶28); and an external electrode (131, 132 – Fig. 2 ¶28) including an electrode layer disposed on the body and connected to the internal electrode (131a, 132a – Fig. 2 ¶28), a plating layer disposed on the electrode layer (131c1, 132c1 – Fig. 2 ¶28), and a conductive resin layer including a conductive metal and a resin (131b, 132b – Fig. 2 ¶89), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including copper (Cu) and a first glass (connection electrode layer – Figure 1 shown above ¶84-¶85), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including silver (Ag) and a second glass (band electrode layer – Figure. 1 shown above ¶84-85), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Figure 1 shown above).
Regarding claim 2, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive metal comprises copper (Cu) (¶91).
Regarding claim 3, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive metal comprises an intermetallic compound (¶98).
Regarding claim 4, Jeong discloses the multilayer electronic component of claim 1, wherein the band electrode layer is not disposed between an extension line of the first surface and an extension line of the second surface (Figure 1 shown above).
Regarding claim 6, Jeong discloses the multilayer electronic component of claim 1, wherein the band electrode layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 7, Jeong discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 9, Jeong discloses the multilayer electronic component of claim 1, wherein the plating layer is not in direct contact with the band electrode layer (Figure 1 shown above; The conductive resin layer covers the entire band electrode layer).
Regarding claim 10, Jeong discloses the multilayer electronic component of claim 1, wherein the plating layer comprises a first plating layer disposed on the connection electrode layer and the conductive resin layer, and a second plating layer disposed on the first plating layer (131c1, 131c2 – Fig. 2 ¶107).
Regarding claim 11, Jeong discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶28) including a dielectric layer (111 – Fig. 2 ¶28) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 2 ¶28), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface, and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape ¶28); and an external electrode (131, 132 – Fig. 2 ¶28) including an electrode layer disposed on the body and connected to the internal electrode (131a, 132a – Fig. 2 ¶28), a plating layer disposed on the electrode layer (131c1, 132c1 – Fig. 2 ¶28), and a conductive resin layer (131b, 132b – Fig. 2 ¶89), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including a first conductive metal and a first glass (connection electrode layer – Figure 1 shown above ¶84-¶85), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including a second conductive metal and a second glass (band electrode layer – Figure. 1 shown above ¶84-85), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Figure 1 shown above), and the conductive resin layer includes a third conductive metal and a resin (¶89).
Regarding claim 12, Jeong discloses the multilayer electronic component of claim 11, wherein the band electrode layer is not disposed between an extension line of the first surface and an extension line of the second surface (Figure 1 shown above).
Regarding claim 14, Jeong discloses the multilayer electronic component of claim 11, wherein the band electrode layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 15, Jeong discloses the multilayer electronic component of claim 11, wherein the conductive resin layer is disposed between an extension line of the third surface and an extension line of the fourth surface (Figure 1 shown above).
Regarding claim 16, Jeong discloses the multilayer electronic component of claim 11, wherein the second conductive metal is softer than the first conductive metal (From ¶84-¶85, the electrode layer may include both copper and silver. The first conductive metal may then be copper and the second conductive metal may then be silver. Therefore, the second conductive metal is softer than the first conductive metal).
Regarding claim 17, Jeong discloses the multilayer electronic component of claim 11, wherein the second conductive metal and the first conductive metal are different metals (From ¶84-¶85, the electrode layer may include both copper and silver. The first conductive metal may then be copper and the second conductive metal may then be silver).
Regarding claim 18, Jeong discloses the multilayer electronic component of claim 11, wherein the resin includes an epoxy resin (¶97).
Regarding claim 19, Jeong discloses the multilayer electronic component of claim 11, wherein the second glass includes a glass frit (¶86).
Claim(s) 1, 5, 8, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2021/0065984 A1), hereafter referred to as Oh.
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Figure 2: Examiner modified Fig. 3 of Oh showing extensions lines of the first surface (EL1) and the second surface (EL2). The conductive resin layer (133, 143) is shown to only be disposed on the band electrode layer (131b, 141b) and is not disposed between EL1 and EL2.
Regarding claim 1, Oh discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶35) including a dielectric layer (111 – Fig. 3 ¶36) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 3 ¶45), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface , and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape); and an external electrode including an electrode layer disposed on the body and connected to the internal electrode (130, 140 – Fig. 1 ¶53), a plating layer disposed on the electrode layer (132, 142 – Fig. 3 ¶66), and a conductive resin layer including a conductive metal and a resin (133, 143 – Fig. 3 ¶62-¶64), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including copper (Cu) and a first glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including silver (Ag) and a second glass (131b, 141b – Fig. 3 ¶55 and ¶57-¶58), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Fig. 3).
Regarding claim 5, Oh discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is not disposed between an extension line of the first surface and an extension line of the second surface (133, 143 – Figure 2 shown above and ¶55).
Regarding claim 8, Oh discloses the multilayer electronic component of claim 1, wherein the conductive resin layer is not in direct contact with the connection electrode layer (133, 143 – Figure 2 shown above and ¶55 discloses that the conductive resin layer is only on the band electrode layer. In other words, no portion of the conductive resin layer is shown to be disposed between the extension lines EL1 and EL2).
Regarding claim 11, Oh discloses a multilayer electronic component comprising: a body (110 – Fig. 1 ¶35) including a dielectric layer (111 – Fig. 3 ¶36) and an internal electrode alternately disposed with the dielectric layer in a first direction (121, 122 – Fig. 3 ¶45), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction and connected to the first surface and the second surface, and a fifth surface and a sixth surface opposing each other in a third direction and connected to the first surface, the second surface, the third surface, and the fourth surface (110 – Fig. 1 shows a parallelepiped shape); and an external electrode including an electrode layer disposed on the body and connected to the internal electrode (130, 140 – Fig. 1 ¶53), a plating layer disposed on the electrode layer (132, 142 – Fig. 3 ¶66), and a conductive resin layer (133, 143 – Fig. 3 ¶62-¶64), wherein the electrode layer includes a connection electrode layer disposed on the third surface and the fourth surface and including a first conductive metal and a first glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and a band electrode layer contacting the connection electrode layer, disposed on a portion of the first surface and a portion of the second surface, and including a second conductive metal and a second glass (131a, 141a – Fig. 3 ¶55 and ¶57-¶58), and the conductive resin layer is disposed between the band electrode layer and the plating layer (Fig. 3), and the conductive resin layer includes a third conductive metal and a resin (¶62-¶64).
Regarding claim 13, Oh discloses the multilayer electronic component of claim 11, wherein the conductive resin layer is not disposed between an extension line of the first surface and an extension line of the second surface (133, 143 – Figure 2 shown above and ¶55).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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