Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,3-5, 7 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cao et al (2011/0304940 A1).
Cao discloses a voltage protection circuit comprising: a programmable reference voltage circuit (paras 0036-0037 and block 4 in Fig. 7) configured to receive an input voltage and to generate a reference voltage (see last sentence of Abstract); an error amplifier stage (see 33 in Fig.7) coupled to the programmable reference voltage circuit; a voltage limiting circuit (see 34 in Fig. 7, which limits the voltage at the gate of the clamping element S2) coupled to the programmable reference voltage circuit and the error amplifier stage; and a voltage clamping element 2 coupled to the programmable reference voltage circuit, the error amplifier stage and the voltage limiting circuit (see 2 in Fig. 7).
With regard to claims 3-5 and 14 Cao discloses 33 and 331 (a pFET) as an error amplifier in Figs. 8 and 9 (also see paras 0064-0067).
With regard to claim 7, Cao discloses switch 2 in Fig. 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 6, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao et al (2011/0304940A1) in view of Semtech (EP 4 071 812 A1 from PCT 237 of 9-29-25).
Cao discloses a voltage protection circuit comprising: a programmable reference voltage circuit (paras 0036-0037 and block 4 in Fig. 7) configured to receive an input voltage and to generate a reference voltage (see last sentence of Abstract); an error amplifier stage (see 33 in Fig.7) coupled to the programmable reference voltage circuit; a voltage limiting circuit (see 34 in Fig. 7, which limits the voltage at the gate of the clamping element S2) coupled to the programmable reference voltage circuit and the error amplifier stage; and a voltage clamping element 2 coupled to the programmable reference voltage circuit, the error amplifier stage and the voltage limiting circuit (see 2 in Fig. 7).
The voltage protection circuit of Cao differs from the claims by not being specifically said to recite additional details of the dependent claims such as the voltage limit circuit configured to limit the maximum voltage at the voltage clamping element.
Semtech discloses a voltage protection circuit having a voltage limiting circuit 100 for limiting the gate terminal voltage of the clamping circuit (see Fig. 6c and paras 0024-0026) (claim 6) and addresses the FET and diode limitations of claims 15-19. The bypass considerations of claim 2 are conventional practice in the art and the feature is addressed in para 0012.
It would have been obvious to one of ordinary skill to combine the teachings of Cao and Semtech to meet the claims because both teachings are voltage protection circuits having clamping circuits and programmable voltage reference circuits, with the additional features available to persons of ordinary skill to implement the circuits functional with a larger range of discrete electronic device types.
Allowable Subject Matter
Claim 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: claims 8-13 recite different bypass circuit responses and programmable reference circuit variations that have not been taught or been fairly suggested by the prior art of record.
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SWJackson
February 19, 2026
/STEPHEN W JACKSON/ Primary Examiner, Art Unit 2838