DETAILED ACTION
The current Office Action is in response to the papers submitted 07/28/2026. Claims 1, 3, 5 – 7, 9 – 18, and 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5 – 7, 9 – 10, 12, and 14 - 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (Pub. No.: US 2019/0310774) referred to as Oh in view of Nipunage et al. (Pat 11,467,736) referred to as Nipunage in view of Twocentpdx (Programmable ROM) referred to Twocentpdx in view of Lopes et al. (Pub. No.: US 2019/0181864) referred to as Lopes.
Regarding claim 1, Oh teaches tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10] by:
storing a first set of block status data that indicates a status of each block of the plurality of blocks [G/B BITMAP, Fig 9] in the first memory device [6100, Fig 10], wherein the first set of block status data indicates whether the plurality of blocks are bad blocks [G/B BITMAP, Fig 9];
analyzing the first block status data to determine if a block is bad or not [Fig 8; G/B BITMAP, Fig 9; Paragraphs 0105 – 0124; The bad block metadata is used to manage data in the memory];
the first memory device is a non-volatile memory device [6110, Fig 10];
a controller [6120, Fig 10] to which the first memory device is coupled [6110, Fig 10].
However, Oh may not specifically disclose the limitations of storing, in a memory location external to the first memory device, a second set of block status data that indicates the status of each block of the plurality of blocks, wherein the second set of block status data indicates whether the plurality of blocks are bad blocks, at particular time intervals and in accordance with a repeating pattern, determining whether the first set of block status data has been corrupted by comparing the first set of block status data to the second set of block status data, and in response to determining that the first set of block status data has been corrupted, overwriting the first set of block status data with the second set of block status data, the memory location is within a one-time programmable (OTP) memory external to the first memory, the storing of the second set of block status data is carried out by a controller during operation of the controller, and a difference between the first set of block status data of the first memory device and the second set of block status data of the OTP memory indicates a latch upset has occurred in the first memory device.
Nipunage teaches storing, in a memory location [270M, Fig 2] external to the first memory device [260, Fig 2; Column 12, Lines 35 – 54; A second copy of the metadata is stored in a target location separate from the first metadata in a source location], a second set of block status data that indicates the status of each block of the plurality of blocks, wherein the second set of block status data indicates whether the plurality of blocks are bad blocks, at particular time intervals and in accordance with a repeating pattern [Fig 4; The comparison at step 416 is performed during time intervals of a write between the start and end of the write operation. Step 416 is also performed in the time interval between steps 414 and 416. The comparison is part of the repeating pattern of the method of 400 which is repeated for each write command], determining whether the first set of block status data has been corrupted by comparing the first set of block status data to the second set of block status data, and in response to determining that the first set of block status data has been corrupted, overwriting the first set of block status data with the second set of block status data, the memory location is within a memory external to the first memory device, the storing of the second set of block status data is carried out by a controller during operation of the controller [210, 270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; Column 7, Lines 58 – 67; Column 8, Lines 1 – 16; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. The metadata being compared shows the metadata was created before the comparison and the comparison is in response to the creation of the metadata. Either copy of the metadata can be considered corrupted or invalid as a result of the comparison and then the valid metadata is used to replace the invalid metadata. The operations of storing and comparing are performed by the controller using modules 214 and 220].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Nipunage in Oh, because it provides for redundancy by creating a backup of data and verifying the backup.
However, Oh in view of Nipunage may not specifically disclose the limitation(s) of the memory location is within a one-time programmable (OTP) memory external to the first memory device and a difference between the first set of block status data of the first memory device and the second set of block status data of the OTP memory indicates a latch upset has occurred in the first memory device.
Twocentpdx discloses the memory location is within a one-time programmable (OTP) memory [One time programmable memory, Page 2].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Twocentpdx in Oh in view of Nipunage because it allows the identification of bad blocks of memory after manufacture when the memory is first used which can identify blocks that went bad during manufacture and after manufacture and then stored in memory allowing the system to access an immutable list of bad blocks from when the memory was first used.
However, Oh in view of Nipunage in view of Twocentpdx may not specifically disclose the limitation(s) of a difference in the first and second set of block status data of the OTP memory and the first memory device indicates a latch upset has occurred in the first memory device.
Lopes discloses a difference in the first and second set of block status data of the OTP memory and the first memory device indicates a latch upset has occurred in the first memory device [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event. Oh teaches the first memory device is non-volatile. Twocentpdx discloses the memory location is OTP which is immutable. The comparison disclosed by Lopes would indicate any difference would be due to a latch upset event in the first memory of Oh since the OTP memory of Twocentpdx is immutable].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lopes in Oh in view of Nipunage in view of Twocentpdx, because it allows the system to be tolerant to errors from radiation [Paragraphs 0006 and 0010].
Regarding claim 3, Nipunage teaches the memory location is within a controller and the controller is configured to store the second set of block status data in a register of the controller [222A or 222M, Fig 2; Column 8, Lines 47 – 61; The controller receives the second set of block status metadata and stores the data in a memory register allowing the controller to then write the second set of block status metadata to the external memory location].
Regarding claim 5, Oh teaches tagging the one of the plurality of blocks as the bad block comprises changing its status from a good block to a bad block [Paragraphs 0012, 0063, 0101, 0105, Fig 9; Blocks are determined to be good or bad. When a block is determined to be bad the bitmap is changed for the block to indicate it is no longer good and is bad by switching from 0 to 1].
Regarding claim 6, Oh teaches tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad].
Nipunage discloses in response to the first set of block status data matching the second set of block status data, preventing the first set of block status data from being overwritten [418, Fig 4; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. The Yes outcome in step 418 prevents data from being overwritten for the time being not overwriting any data].
Regarding claim 7, Oh teaches tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
Nipunage discloses in response to the first set of block status data being different than the second set of block status data, writing over the first set of block status data with the second set of block status data [Column 2, Lines 51 – 64; Column 8, Lines 32 – 46; Column 7, Lines 58 – 67; Column 8, Lines 1 – 16; Column 13, Lines 64 – 67; Column 14, Lines 1 – 20; Column 14, Lines 55 – 67; Column 15, Lines 1 – 5; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of Metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. When the two versions of metadata do not match one version is used to overwrite the other version of metadata. The UUID is another version of metadata and when metadata of different data does not match one version of UUID metadata is replaced with another version of the UUID metadata].
Regarding claim 9, Lopes discloses in response to determining that the latch upset event has occurred, setting a flag [Paragraph 0021, 0051 - 0052, Figs 4 – 7; The Error signal(s) are the flags indicating the single even upset (latch upset event) has occurred].
Regarding claim 10, Oh teaches tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
Nipunage discloses determining that an error event on a first set of status data has occurred [Column 2, Lines 51 – 64; Column 8, Lines 32 – 46; Column 13, Lines 64 – 67; Column 14, Lines 1 – 20; Column 14, Lines 55 – 67; Column 15, Lines 1 – 5; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. The status data that is not the majority is where the error is determined to occur].
Lopes discloses the error is a latch upset event [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event].
Regarding claim 12, Oh teaches a non-volatile memory device [6110, Fig 10] comprising a plurality of blocks of memory [Fig 9; Each chip is comprised of planes divided into blocks of memory]; and
a controller [6120, Fig 10] coupled to the non-volatile memory device [6110, Fig 10] and configured to:
write a first set of block status data [G/B BITMAP, Fig 9] to the non-volatile memory device [6110, Fig 10];
read the first set of block status data from the non-volatile memory device, wherein the first set of block status data indicates whether the plurality of blocks are bad blocks, and wherein the first set of block status data indicates a status of each block of the plurality of blocks in the non-volatile memory device [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad], and
analyzing the first block status data to determine if a block is bad or not [Fig 8; G/B BITMAP, Fig 9; Paragraphs 0105 – 0124; The bad block metadata is used to manage data in the memory].
However, Oh may not specifically disclose the limitation of reading a second set of block status data from a one-time programmable (OTP) memory, wherein the second set of block status data read from the OTP memory is non-changing, wherein the second set of block status data read from the OTP indicates whether the plurality of blocks are bad blocks, wherein the second set of block status data read from the OTP indicates the status of each block of the plurality of blocks of memory, and wherein a difference in the first set of block status data of the non-volatile memory device and the second set of block status data read from the OTP memory indicates a latch upset event has occurred in the non-volatile memory device, at particular time intervals and in accordance with a repeating pattern, determining whether the first set of block status data has been corrupted by comparing the first set of block status data to the second set of block status data read from the OTP, and in response to the first set of block status data being different than the second set of block status data read from the OTP, write the second set of block status data read from the OTP over the first set of block status data in the non-volatile memory device.
Nipunage discloses reading a second set of block status data from a memory [270M, Fig 2; Column 12, Lines 35 – 54; A second copy of the metadata is stored in a target location separate from the first metadata in a source location], wherein the second set of block status data read from the memory indicates whether the plurality of blocks are bad blocks, wherein the second set of block status data read from the memory indicates the status of each block of the plurality of blocks of memory, compare the first set of block status data to the second set of block status data from the memory, at particular time intervals and in accordance with a repeating pattern [Fig 4; The comparison at step 416 is performed during time intervals of a write between the start and end of the write operation. Step 416 is also performed in the time interval between steps 414 and 416. The comparison is part of the repeating pattern of the method of 400 which is repeated for each write command], determining whether the first set of block status data has been corrupted by comparing the first set of block status data to the second set of block status data read from the memory, and in response to the first set of block status data being different than the second set of block status data read from the memory, write the second set of block status data read from the memory over the first set of block status data in the non-volatile memory device [270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; Column 2, Lines 51 – 64; Column 7, Lines 58 – 67; Column 8, Lines 1 – 16 and 32 – 46; Column 13, Lines 64 – 67; Column 14, Lines 1 – 20; Column 14, Lines 55 – 67; Column 15, Lines 1 – 5; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. The metadata being compared shows the metadata was created before the comparison and the comparison is in response to the creation of the metadata. Either copy of the metadata can be considered corrupted or invalid as a result of the comparison and then the valid metadata is used to replace the invalid metadata].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Nipunage in Oh, because it provides for redundancy by creating a backup of data and also verifying the backup.
However, Oh in view of Nipunage may not specifically disclose the limitation of reading data from a one-time programmable (OTP) memory wherein the data read from the OTP is non-changing and wherein a difference in the first set of block status data of the non-volatile memory device and the second set of block status data read from the OTP memory indicates a latch upset event has occurred in the non-volatile memory device.
Twocentpdx reading data from a one-time programmable (OTP) memory wherein the data read from the OTP is non-changing [One time programmable memory, Page 2].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Twocentpdx in Oh in view of Nipunage because it allows the identification of bad blocks of memory after manufacture when the memory is first used which can identify blocks that went bad during manufacture and after manufacture and then stored in memory allowing the system to access an immutable list of bad blocks from when the memory was first used.
However, Oh in view of Nipunage in view of Twocentpdx may not specifically disclose the limitation(s) of wherein a difference in the first set of block status data of the non-volatile memory device and the second set of block status data read from the OTP memory indicates a latch upset event has occurred in the non-volatile memory device.
Lopes discloses a difference in the first set of block status data of the non-volatile memory device and the second set of block status data read from the OTP memory indicates a latch upset event has occurred in the non-volatile memory device [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event. Oh teaches that the first memory device is non-volatile. Twocentpdx discloses the memory location is OTP which is immutable. The comparison disclosed by Lopes would indicate any difference would be due to a latch upset event in the first memory which is non-volatile and can change of Oh since the OTP memory of Twocentpdx is immutable].
Regarding claim 14, Oh teaches the controller [6120, Fig 10] tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
Nipunage discloses comparing metadata about data to determine when an error occurred regarding the data [270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices].
Lopes discloses setting a flag indicating occurrence of a latch upset event in response to the first set of block data being different than the second set of block data read from the OTP [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event. The Error signal(s) are the flags indicating the single even upset (latch upset event) has occurred. Twocentpdx discloses the memory location is OTP which is immutable. The comparison disclosed by Lopes would indicate any difference would be due to a latch upset event in the first memory of Oh since the OTP memory of Twocentpdx is immutable].
Regarding claim 15, Oh teaches the controller [6120, Fig 10] tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
Nipunage discloses comparing metadata about data to determine when an error occurred regarding the data [270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices].
Lopes discloses in response to the first set of block status data matching the second set of block status data read from the OTP, determining an absence of a latch upset event on the non-volatile memory device [Paragraph 0021, 0051 - 0052, Figs 4 – 7; When the two sets of data match an error is not detected which indicates there is no single even upset which is considered the latch upset event. Twocentpdx discloses the memory location is OTP which is immutable. The comparison disclosed by Lopes would indicate any difference would be due to a latch upset event in the first memory of Oh since the OTP memory of Twocentpdx is immutable].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (Pub. No.: US 2019/0310774) referred to as Oh in view of Nipunage et al. (Pat 11,467,736) referred to as Nipunage in view of Twocentpdx (Programmable ROM) referred to Twocentpdx in view of Lopes et al. (Pub. No.: US 2019/0181864) referred to as Lopes as applied to claim 1 above, and further in view of Marcu et al. (Pub. No.: US 2022/0405601) referred to as Marcus.
Regarding claim 11, Oh teaches storing and tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
However, Oh in view of Nipunage in view of Twocentpdx in view of Lopes may not specifically disclose the limitation of storing data within complementary metal-oxide semiconductor (CMOS) latches of the first memory device.
Marcu discloses storing data within complementary metal-oxide semiconductor (CMOS) latches of the first memory device [200, Fig 2; 304, Fig 3; 406 and 410, Fig 4; Paragraph 0032; The latches are part of a CMOS chip making the CMOS latches store data of the memory. The CMOS latches are in a CMOS Chip that is part of a memory device such as 200 or 304].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Marcu in Oh in view of Nipunage in view of Twocentpdx in view of Lopes, because CMOS latches allow for low power consumption and high integration density in memory.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (Pub. No.: US 2019/0310774) referred to as Oh in view of Nipunage et al. (Pat 11,467,736) referred to as Nipunage in view of Twocentpdx (Programmable ROM) referred to Twocentpdx in view of Lopes et al. (Pub. No.: US 2019/0181864) referred to as Lopes as applied to claim 12 above, and further in view of Marcu et al. (Pub. No.: US 2022/0405601) referred to as Marcus.
Regarding claim 13, Oh teaches storing and tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
However, Oh in view of Nipunage in view of Twocentpdx in view of Lopes may not specifically disclose the limitation of storing data within complementary metal-oxide semiconductor (CMOS) latches of the first memory device.
Marcu discloses storing data within complementary metal-oxide semiconductor (CMOS) latches of the first memory device [200, Fig 2; 304, Fig 3; 406 and 410, Fig 4; Paragraph 0032; The latches are part of a CMOS chip making the CMOS latches store data of the memory. The CMOS latches are in a CMOS Chip that is part of a memory device such as 200 or 304].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Marcu in Oh in view of Nipunage in view of Twocentpdx in view of Lopes, because CMOS latches allow for low power consumption and high integration density in memory.
Claim(s) 16 – 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (Pub. No.: US 2019/0310774) referred to as Oh in view of Nipunage et al. (Pat 11,467,736) referred to as Nipunage in view of Ayyapureddi et al. (Pub. No.: US 2023/0229348) referred to as Ayyapureddi in view of Lopes et al. (Pub. No.: US 2019/0181864) referred to as Lopes.
Regarding claim 16, Oh teaches a non-volatile memory device [6110, Fig 10] comprising a plurality of blocks of memory [Fig 9; Each chip is comprised of planes divided into blocks of memory]; and
a controller [6120, Fig 10] coupled to the non-volatile memory device [6110, Fig 10] and configured to:
load the first set of clock status data into the non-volatile memory device [G/B BITMAP, Fig 9; The bitmap information is created and loaded in the memory device];
read a first set of block status data from the non-volatile memory device, wherein the first set of block status data indicates whether the plurality of blocks are bad blocks, and wherein the first set of block status data indicates a status of each block of the plurality of blocks in the non-volatile memory device [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad].
However, Oh may not specifically disclose the limitations of loading a first set of block status data into latches of memory, reading a second set of block status data from a memory, wherein the second set of block status data indicates whether the plurality of blocks are bad blocks, and wherein the second set of block status data indicates the status of each block of the plurality of blocks of memory, compare the first set of block status data to the second set of block status data at particular time intervals and in accordance with a repeating pattern, and in response to determining that the first set of block status data does not match the second set of block status data, reloading the first set of block status data by overwriting the first set of block status data stored in the latches of the non-volatile memory device with the second set of block status data stored in an additional memory device, wherein a difference between the first set of block status data of the non-volatile memory device, and the second set of block status data of the register of the controller indicates a latch upset event has occurred in the non-volatile memory device.
Nipunage discloses reading a second set of block status data from a memory, wherein the second set of block status data indicates whether the plurality of blocks are bad blocks, and wherein the second set of block status data indicates the status of each block of the plurality of blocks of memory, compare the first set of block status data to the second set of block status data at particular time intervals and in accordance with a repeating pattern [Fig 4; The comparison at step 416 is performed during time intervals of a write between the start and end of the write operation. Step 416 is also performed in the time interval between steps 414 and 416. The comparison is part of the repeating pattern of the method of 400 which is repeated for each write command], and in response to determining that the first set of block status data does not match the second set of block status data, reloading the first set of block status data by overwriting the first set of block data stored in the non-volatile memory device with block status data stored in an additional memory device, wherein a difference between the first set of block status data of the non-volatile memory device, and the second set of block status data of the register of the controller indicates a negative event has occurred in the non-volatile memory device [270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; Column 2, Lines 51 – 64; Column 7, Lines 58 – 67; Column 8, Lines 1 – 16; Column 8, Lines 32 – 46; Column 13, Lines 64 – 67; Column 14, Lines 1 – 20; Column 14, Lines 55 – 67; Column 15, Lines 1 – 5; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices. The storage device with the lower count value indicates a negative event occurred with the storage device such as a dropped write. UUID is another version of metadata. When the metadata does not match one of the metadata is used to overwrite the other metadata].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Nipunage in Oh, because it provides for redundancy by creating a backup of data and also verifying the backup.
However, Oh in view of Nipunage may not specifically disclose the limitation of storing block status data in latches and the difference indicates a latch upset even has occurred.
Ayyapureddi discloses storing block status data in latches [Paragraph 0042; Metadata is stored in latches in memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Ayyapureddi in Oh in view of Nipunage, because latches are a fundamental storage mechanism in the art that one of ordinary skill in the art would understand and have a high level of predictability to store data.
However, Oh in view of Nipunage in view of Ayyapureddi may not specifically disclose the limitation(s) of the difference indicates a latch upset even has occurred.
Lopes discloses the difference indicates a latch upset even has occurred [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lopes in Oh in view of Nipunage in view of Ayyapureddi, because it allows the system to be tolerant to errors from radiation [Paragraphs 0006 and 0010].
Regarding claim 17, Oh teaches the controller [6120, Fig 10] is configured to prevent access to any block of memory that is determined to be a bad block based on the block status data [Paragraph 0063, 0101, and 0129; Bad blocks are not used and replaced with good normal blocks].
Regarding claim 20, Oh teaches the controller [6120, Fig 10] tracking a block status of each of a plurality of blocks [G/B BITMAP, Fig 9; Each bit in the bitmap indicates if a block of memory is good or bad] of a first memory device [6100, Fig 10].
Nipunage discloses comparing metadata about data to determine when an error occurred regarding the data [270M, 272M, 260, 262, 270A, and 272A, Fig 2; 402, 404, 406, and 416, Fig 4; 502, 504, and 506, Fig 5; 602, 604, 606, 608, 610, and 614, Fig 6A; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in different storage devices and then comparing the versions of the metadata from the different storage devices.
Lopes discloses the controller inferring that a latch upset event has occurred in response to the first set of block data being different than the second set of block data. [Paragraph 0021, 0051 - 0052, Figs 4 - 7; The error is based on the comparison of data not resulting in a match between the data which is an indication of a single event upset which is considered the latch upset event].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (Pub. No.: US 2019/0310774) referred to as Oh in view of Nipunage et al. (Pat 11,467,736) referred to as Nipunage in view of Ayyapureddi et al. (Pub. No.: US 2023/0229348) referred to as Ayyapureddi in view of Lopes et al. (Pub. No.: US 2019/0181864) referred to as Lopes as applied to claim 16 above, and further in view of Twocentpdx (Programmable ROM) referred to Twocentpdx.
Regarding claim 18, Nipunage discloses the additional memory device [Column 2, Lines 51 – 64; Column 7, Lines 58 – 67; Column 8, Lines 1 – 16 and 32 – 46; Column 13, Lines 64 – 67; Column 14, Lines 1 – 20; Column 14, Lines 55 – 67; Column 15, Lines 1 – 5; The bad block bitmap information in Oh is metadata. Nipunage discloses storing copies of metadata in difference storage devices and then comparing the versions of the metadata from the different storage devices].
However, Oh in view of Nipunage in view of Ayyapureddi in view of Lopes may not specifically disclose the limitation of storing data in and accessing the data from a one-time programmable (OTB) memory.
Twocentpdx discloses storing data in and accessing the data from a one-time programmable (OTB) memory [One time programmable memory, Page 2].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Twocentpdx in Oh in view of Nipunage in view of Ayyapureddi in view of Lopes because it allows the identification of bad blocks of memory after manufacture when the memory is first used which can identify blocks that went bad during manufacture and after manufacture and then stored in memory allowing the system to access an immutable list of bad blocks from when the memory was first used.
Response to Arguments
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive.
The applicant argues on page 9, regarding the independent claims, that Oh and Nipunage fail to teach comparing status data at particular time intervals and in accordance with a repeating pattern and the addition of Nipunage in Oh would introduce a delay in Oh. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The rejections above have been updated to show how Nipunage teaches the argued limitations. Oh is not relied upon to teach the particular time intervals or the repeating pattern limitation. The comparing in step 416 of Nipunage is performed in the time interval of a write operation and also in the time interval between steps 414 and 418. Step 416 is also performed in accordance with a repeating pattern of the process 400 in figure 4. Every time a write command is received the same process is repeated which includes step 416. This shows step 416 is performed in a time interval that is part of a repeating pattern which is process 400 in figure 4 for each write.
Any combination of references is going to have some trade off. This alone is not enough to say the combination teaches away from one of the references. The checking of a good block in Oh requires some level of comparing information to know if a block is good or not. Nipunage teaches a similar comparing operation to check if data is good or not. If there was a delay introduced, it would be negligible and does not teach away from Oh.
The applicant argues on page 10, regarding the independent claims, that Twocentpdx fails to remedy the argued deficiencies of prior art and that the OTP of Twocentpdx cannot be combined with the prior art. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding the prior art explaining how the prior art teaches the argued limitation. Nipunage discloses multiple target storage locations to store metadata. Before metadata is updated the first target storage location can be the OTP memory and used to store metadata. A comparison of the first target metadata location in OTP memory and the source metadata location can then be performed to see if something changed erroneously in the source metadata location.
The applicant argues on ages 10 – 11, with regard to the independent claims, that Lopes fails to overcome the argued deficiencies of the prior art and that it would not be obvious to combine Lopes with the prior art since Lopes is concerned with preventing the propagation of errors where Oh is concerned with managing blocks of memory. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding the prior art explaining how the prior art teaches the argued limitation. Lopes concern with propagation of error when writing data is related to managing blocks of memory. Lopes teaches a comparison of data to identify a latch upset event which is what the comparison in the claims is used to identify. Nipunage uses a comparison of metadata to determine which version of metadata is valid. This shows Lopes is related and relevant to the claims and also the other related prior art in the rejection.
The applicant argues on pages 11 – 12, regarding claim 11, that Marcu fails to cure the argued deficiencies of the other prior art in the base claim of claim 11. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding the prior art explaining how the prior art teaches the argued limitation. The rejection of claim 11 is maintained based in part on the rejection of the base claim.
The applicant argues on page 12, regarding claim 13, that Marcu fails to cure the argued deficiencies of the other prior art in base claim 12. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding the prior art explaining how the prior art teaches the argued limitation. The rejection of claim 13 is maintained based in part on the rejection of the base claim.
The applicant argues on pages 12 – 15, regarding claims 16 – 17 and 20 that the prior art of Oh in view of Nipunage in view of Ayyapureddi in view of Lopes fails to teach the claimed limitations. The arguments against Oh, Nipunage, and Lopez are the same arguments argued above regarding the independent claims. Ayyapureddi is argued as not curing the deficiencies of the additional prior art and not being not related to the same concern as Oh.
The examiner has responded to the arguments against Oh, Nipunage, and Lopes showing how they teach certain limitations of the claims. The latch of Ayyapureddi is a well-known device in the art of computer memory that one of ordinary skill in the art would understand how they work and their benefits. There would also be a high level of predicted result of using a latch since their use is well known and understood in the art. Being directed to a different goal alone does not prevent a reference from being combined with another reference.
The applicant argues on pages 15 – 16, regarding claim 18, that Twocentpdx fails to cure the argued deficiencies of the other prior art in base claim 16. After careful consideration of the applicant's arguments the examiner respectfully disagrees
The examiner has responded to the arguments above showing how the prior references teach the argued limitations. The rejection of claim 18 is maintained based in part on the rejections of base claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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