Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 respectively of U.S. Patent No. 11,416,442. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the US Patent No. 11,416,442 are similar in scope to claims 1-20 of the present application with only obvious wording variations.
Present Application
Pat No. 11,416,442
An integrated circuit comprising: a state machine configured to, in response to a received first signal, execute a first function of a plurality of functions;
and wherein the integrated circuit is arranged to modify a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
2. The integrated circuit of claim 1, wherein the integrated circuit is arranged to modify said mapping between the first signal and the first function in dependence on the execution of the first function at the state machine.
3. The integrated circuit of claim 1, wherein the integrated circuit is arranged to re-map the first signal to the second function at least one of: in dependence on the number of times the first function is executed at the state machine; and as part of the execution of the first function at the state machine.
4. The integrated circuit of claim 1, wherein the mapping comprises a first pointer associated with the first signal, which first pointer points to the first function.
5. The integrated circuit of claim 4, wherein the integrated circuit is arranged to re-map the first signal to the second function by one of: associating a second pointer with the first signal in place of the first pointer, which second pointer points to the second function; and modifying the first pointer to point to the second function.
6. The integrated circuit of claim 1, wherein the integrated circuit comprises an event queue configured to receive a plurality of event indices, the state machine being configured to read event indices on the event queue, wherein the reading by the state machine of an event index from the event queue causes the state machine to execute at least one of the plurality of functions.
7. The integrated circuit of claim 6, wherein said mapping comprises writing a first event index to the event queue, which first event index when read by the state machine causes the state machine to execute the first function.
8. The integrated circuit of claim 7, wherein the first event index comprises a first pointer associated with the first signal, which first pointer points to the first function.
9. The integrated circuit of claim 7, wherein the re-mapping of the first signal to a second function comprises writing a second event index to the event queue, which second event index when read by the state machine causes the state machine to execute the second function.
10. The integrated circuit of claim 6, wherein where the first function is a large function, the integrated circuit is arranged to break the first function into smaller functions comprising a first smaller function and a second smaller function, and to associate a first smaller function pointer with the first smaller function and a second smaller function pointer with the second smaller function such that the first and second smaller function pointers point to the respective smaller functions; the integrated circuit being arranged, on receiving the first signal, to write an event index comprising the first smaller function pointer to the event queue such that the state machine executes the first smaller function; and subsequently to write an event index comprising the second smaller function pointer to the event queue such that the state machine executes the second smaller function after the execution of the first smaller function.
11. The integrated circuit of claim 6, wherein where the first function is a large function, it can be broken down into smaller functions for rescheduling in dependence on at least one of: whether the number of event indices on the event queue is above a given threshold, and whether the large function is time-critical.
12. The integrated circuit of claim 10, wherein the integrated circuit is arranged to write the event index comprising the second smaller function pointer to the event queue during or at the end of execution of the first smaller function.
13. The integrated circuit of claim 1, further comprising a mapping interface configured to perform the mapping between the first signal and the first function.
14. The integrated circuit of claim 1, further comprising a memory configured to store the plurality of functions.
15. The integrated circuit of claim 13, wherein the mapping interface comprises a communications interface for interfacing between a host system and the state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.
16. The integrated circuit of claim 15, wherein the integrated circuit comprises an event queue configured to receive a plurality of event indices, the state machine being configured to read event indices on the event queue, wherein the reading by the state machine of an event index from the event queue causes the state machine to execute at least one of the plurality of functions, and wherein the event slot is arranged to communicate with the state machine by placing at least one event index on the event queue.
17. The integrated circuit of claim 15, wherein the event slot comprises: a mask register for setting mask values, and a reference register for storing reference information.
18. The integrated circuit of claim 15, wherein the communications interface comprises a plurality of event slots, and at least two of the plurality of event slots are addressed from the host system using different address locations.
19. A method of executing at least one function in response to a signal received by an integrated circuit, the integrated circuit comprising a state machine,
the method comprising: receiving a first signal at the integrated circuit; executing at the state machine a first function of a plurality of functions in response to the received first signal; modifying at the integrated circuit a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit comprising: a state machine
configured to, in response to a received first signal, execute a first function of a plurality of functions; wherein the integrated circuit is arranged to modify a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
1. An integrated circuit comprising: a state machine; machine is configured to, in response to a received first signal, execute a first function of the plurality of functions; and wherein the integrated circuit is arranged to modify a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
2. The integrated circuit of claim 1, wherein the integrated circuit is arranged to modify said mapping between the first signal and the first function in dependence on the execution of the first function at the state machine.
3. The integrated circuit of claim 1, wherein the integrated circuit is arranged to re-map the first signal to the second function at least one of: in dependence on the number of times the first function is executed at the state machine; and as part of the execution of the first function at the state machine.
4. The integrated circuit of claim 1, wherein the mapping comprises a first pointer associated with the first signal, which first pointer points to the first function.
5. The integrated circuit of claim 4, wherein the integrated circuit is arranged to re-map the first signal to the second function by one of: associating a second pointer with the first signal in place of the first pointer, which second pointer points to the second function; and modifying the first pointer to point to the second function.
6. The integrated circuit of claim 1, wherein the integrated circuit comprises an event queue configured to receive a plurality of event indices, the state machine being configured to read event indices on the event queue, wherein the reading by the state machine of an event index from the event queue causes the state machine to execute at least one of the plurality of functions.
7. The integrated circuit of claim 6, wherein said mapping comprises writing a first event index to the event queue, which first event index when read by the state machine causes the state machine to execute the first function.
8. The integrated circuit of claim 7, wherein the first event index comprises a first pointer associated with the first signal, which first pointer points to the first function.
9. The integrated circuit of claim 7, wherein the re-mapping of the first signal to a second function comprises writing a second event index to the event queue, which second event index when read by the state machine causes the state machine to execute the second function.
10. The integrated circuit of claim 6, wherein where the first function is a large function, the integrated circuit is arranged to break the first function into smaller functions comprising a first smaller function and a second smaller function, and to associate a first smaller function pointer with the first smaller function and a second smaller function pointer with the second smaller function such that the first and second smaller function pointers point to the respective smaller functions; the integrated circuit being arranged, on receiving the first signal, to write an event index comprising the first smaller function pointer to the event queue such that the state machine executes the first smaller function; and subsequently to write an event index comprising the second smaller function pointer to the event queue such that the state machine executes the second smaller function after the execution of the first smaller function.
11. The integrated circuit of claim 6, wherein where the first function is a large function, it can be broken down into smaller functions for rescheduling in dependence on at least one of: whether the number of event indices on the event queue is above a given threshold, and whether the large function is time-critical.
12. The integrated circuit of claim 10, wherein the integrated circuit is arranged to write the event index comprising the second smaller function pointer to the event queue during or at the end of execution of the first smaller function.
13. The integrated circuit of claim 1, further comprising a mapping interface configured to perform the mapping between the first signal and the first function.
14. The integrated circuit of claim 13, wherein the mapping interface comprises at least one of a hardware interface and a software interface.
15. The integrated circuit of claim 13, wherein the mapping interface comprises a communications interface for interfacing between a host system and the state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.
16. The integrated circuit of claim 15, wherein the integrated circuit comprises an event queue configured to receive a plurality of event indices, the state machine being configured to read event indices on the event queue, wherein the reading by the state machine of an event index from the event queue causes the state machine to execute at least one of the plurality of functions, and wherein the event slot is arranged to communicate with the state machine by placing at least one event index on the event queue.
17. The integrated circuit of claim 15, wherein the event slot comprises: a mask register for setting mask values, and a reference register for storing reference information.
18. The integrated circuit of claim 15, wherein the communications interface comprises a plurality of event slots, and at least two of the plurality of event slots are addressed from the host system using different address locations.
19. A method of executing at least one function in response to a signal received by an integrated circuit, the integrated circuit comprising first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit comprising: a state machine; integrated circuit is arranged to modify a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function.
In re Karlson, 136 USPQ 189 (ccPA 1963).
Allowable Subject Matter
Claims 1-20 are allowable over the prior of records.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 1 and 19-20 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the integrated circuit is arranged to modify a mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function (claims 1, 19-20).
Conclusion
All claims are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Goodnow et al. (US No. 7,065,733) disclose a method includes the steps of modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; generating a programmable logic device netlist from differences in the high-level design and the high-level modified design; and installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.
Mergard (US No. 6,327,508) discloses a programmable state machine provides a capability of dynamically changing state-machine functions. State machine programming may be accomplished dynamically by a processor through a plurality of mask registers. The plurality of mask registers provide for selective enabling and disabling of input values and transition values of the programmable state machine.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
All Internet e-mail communications will be made of record in the application file. PTO employees do not engage in Internet communications where there exists a possibility that sensitive information could be identified or exchanged unless the record includes a properly signed express waiver of the confidentiality requirements of 35 U.S.C. 122. This is more clearly set forth in the Interim Internet Usage Policy published in the Official Gazette of the Patent and Trademark on February 25, 1997 at 1195 OG 89.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see hop://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175