Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: applicant’s response filed on April 29, 2026.
This application has been examined. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 13-14, 19-20 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Chambers et al. (“Chambers (‘994)”) (US No. 5,796,994) in view of Chambers (“Chamers (‘251)”) (US No. 5,949,251).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Chambers (‘994) and Chambers (‘251) references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Chambers (‘994) discloses an integrated circuit comprising:
a state machine configured to, in response to a received first signal, execute a first function of a plurality of functions (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Chambers (‘994) discloses Abstract + col. 4:66 thru col. 5:16: “A patch mechanism for dynamic modification of the behavior of a state machine” that implemented on an integrated circuit. The state machine circuit is expressly fabricated as an integrated circuit (IC). Col. 6:64 thru col. 7:26: “programmable logic array means for storing a modified transition for an individual state” that stores modified function behaviors for the state machine. The PLA stores multiple modified behaviors (functions). Col. 5:32-48: “user programmable Random Access Memory (RAM) based programmable logic array” thus RAM stores the modified functions.
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and wherein the integrated circuit is arranged to modify a mapping between the first signal and the first function (in Chambers (‘994), Col. 6:64 thru col. 7:26: “logic means coupled to said state machine and to said multiplexer means for signaling said multiplexer means when it is valid to modify said individual state” that this logic means is the mapping interface; it maps incoming state signals to functions (either original or patched). The multiplexer means receives inputs from state machine and PLA that performs the signal-to-function mapping selection), so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a further first signal, the state machine is configured to execute the second function (in Chambers (‘994), Col. 6:64 thru col. 7:26: the state machine executes the function stored in the PLA in response to the signal being received and the mapping logic selecting the appropriate function. Fig. 1: state machine circuit directly connected to multiplexer output that executes the selected function. Col. 6:64 thru col. 7:26 + Claim 1: “logic means…for signaling said multiplexer means when it is valid to modify said individual state to be modified from said unmodified current transition…to said modified transition”. The modification of the mapping is triggered by the state machine's own execution which 'when it is valid' is determined by the state machine reaching a specific execution point. On next receipt of the same signal, the mux selects the patched (second) function. Once modification is signaled, the mux is redirected to the PLA output = remapping. Subsequent identical input causes execution of second (patched) function. Also see col. 5:48 thru col. 6:16). But Chambers (‘994) does not explicitly disclose RAM-based discrete addressable function storage, comparator-based lookup of signal against stored table, and pointer-level modification that overwrites a stored address field. In the same field of endeavor, Chambers (‘251) discloses RAM-based discrete addressable function storage (as shown in Fig. 3A, which is reproduced below for ease of reference and convenience, Chambers (‘251) discloses Abstract + col. 3:42 thru col. 4:3: “A state machine circuit comprising: a combinatorial logic circuit implemented in a semiconductor substrate” that explicitly an integrated circuit. See also claim 1. A programmable patch registers coupled to inputs of said first and second multiplexers that RAM-based patch registers store (state-to-be-patched, next-state-field, output-field) (i.e. plurality of stored functions). Also see col. 6:26-38. Abstract + col. 6:5-62: each patch register entry stores the alternative function (output + next-state),
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comparator-based lookup of signal against stored table (in Chambers (‘251), Col. 6:26-63: “N comparators coupled to said state register and to said n programmable patch registers, said n comparators comparing said state-to-be-patched fields to determine when to modify” thus comparators = mapping interface; they map incoming state signal to the patch register entry (function). Each comparator monitors a signal and maps it to a stored function that direct analog of the claimed mapping interface. First multiplexer…output coupled to supply said state register' and 'second multiplexer…output coupled to supply said output register that the state machine executes the function (produces the output) in response to the comparator selecting the appropriate patch register entry), and pointer-level modification that overwrites a stored address field (in Chambers (‘251), Col. 6:26-63 + Claim 1: “N comparators comparing said state-to-be-patched fields…said control signal…causes said first multiplexer to select between a state value from said combinatorial logic circuit and a state value from…said a programmable patch registers”. The remapping occurs in dependence on execution (state machine reaching the patched state). Subsequent receipt of the same state signal causes execution of the patched (second) function. Chambers (‘251) explicitly stores the remapping data in modifiable RAM registers, allowing runtime updates which directly anticipating the self-modifying mapping concept of claim 1). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Chambers (‘251) with Chambers (‘994) to provide greater flexibility and debuggability in state machine design. Specifically, the ability to re-map a signal from one function to another function without redesigning and refabricating the silicon is highly desirable in complex integrated circuit. This allows designers and end-users to correct errors, optimize behavior, or adapt functionality in the field of a well-known and important goal in the art of state machine design for integrated circuits.
In regard to claim 2, Chambers (‘251) discloses wherein the integrated circuit is arranged to modify said mapping between the first signal and the first function in dependence on the execution of the first function at the state machine (in Chambers (‘251), Col. 6:26-63: “N comparators comparing said state-to-be-patched fields to determine when to modify said state register” that the comparator triggers re-mapping when the state machine reaches the patched state = in dependence on execution of the first function. Directly anticipated). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Chambers (‘251) with Chambers (‘994) to provide greater flexibility and debuggability in state machine design. Specifically, the ability to re-map a signal from one function to another function without redesigning and refabricating the silicon is highly desirable in complex integrated circuit. This allows designers and end-users to correct errors, optimize behavior, or adapt functionality in the field of a well-known and important goal in the art of state machine design for integrated circuits.
In regard to claim 3, Chambers (‘251) discloses wherein the integrated circuit is arranged to re-map the first signal to the second function at least one of: in dependence on the number of times the first function is executed at the state machine; and as part of the execution of the first function at the state machine (in Chambers (‘251), Col. 6:26-63: patch registers are RAM-based and updatable during runtime. The comparator triggers the re-mapping upon each instance that the patched state is reached that after any desired number of executions. Further, the re-mapping occurs during the state machine's transition through the patched state (i.e. as part of execution of the first function)). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Chambers (‘251) with Chambers (‘994) to provide greater flexibility and debuggability in state machine design. Specifically, the ability to re-map a signal from one function to another function without redesigning and refabricating the silicon is highly desirable in complex integrated circuit. This allows designers and end-users to correct errors, optimize behavior, or adapt functionality in the field of a well-known and important goal in the art of state machine design for integrated circuits.
In regard to claim 4, Chambers (‘251) discloses wherein the mapping comprises a first pointer associated with the first signal, which first pointer points to the first function (in Chambers (‘251), Col. 6:26-53: Each patch register contains a “state-to-be-patched field” (i.e. the signal identifier) and a “next state field” (i.e. pointer to the function/next state). The patch register entry is precisely a pointer from signal to function. Chambers ('251) teaches a register-stored pointer mapping). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Chambers (‘251) with Chambers (‘994) to provide greater flexibility and debuggability in state machine design. Specifically, the ability to re-map a signal from one function to another function without redesigning and refabricating the silicon is highly desirable in complex integrated circuit. This allows designers and end-users to correct errors, optimize behavior, or adapt functionality in the field of a well-known and important goal in the art of state machine design for integrated circuits.
In regard to claim 5, Chambers (‘251) discloses wherein the integrated circuit is arranged to re-map the first signal to the second function by one of: associating a second pointer with the first signal in place of the first pointer, which second pointer points to the second function; and modifying the first pointer to point to the second function (in Chambers (‘251), Col. 6:26-63: the patch registers are writable into programmable patch registers that the next state field (i.e. first pointer) can be overwritten to point to a second function. Chambers ('251) in claim 1: “N programmable patch registers” with “next state field” meant modifiable first pointer. Alternatively, a new patch register entry meant second pointer). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Chambers (‘251) with Chambers (‘994) to provide greater flexibility and debuggability in state machine design. Specifically, the ability to re-map a signal from one function to another function without redesigning and refabricating the silicon is highly desirable in complex integrated circuit. This allows designers and end-users to correct errors, optimize behavior, or adapt functionality in the field of a well-known and important goal in the art of state machine design for integrated circuits.
In regard to claim 13, Chambers (‘994) discloses further a mapping interface configured to perform the mapping between the first signal and the first function (in Chambers (‘994), Col. 6:64 thru col. 7:26: “logic means coupled to said state machine and to said multiplexer means for signaling said multiplexer means when it is valid to modify said individual state” that this logic means is the mapping interface; it maps incoming state signals to functions (either original or patched). The multiplexer means receives inputs from state machine and PLA that performs the signal-to-function mapping selection)
In regard to claim 14, Chambers (‘994) discloses further a memory configured to store the plurality of functions (in Chambers (‘994), Col. 5:32-48: “user programmable Random Access Memory (RAM) based programmable logic array” thus RAM stores the modified functions.
Independent claims 19 (method) and 20 (non-transitory computer-readable medium) recite the same operative limitations as an integrated circuit of claim 1 in method and medium form respectively. The integrated circuit/method/medium distinction does not impart patentability where the underlying operative steps are the same. See MPEP § 2114. Therefore, claims 19 and 20 are rejected on the same basis and mapping as claim 1 above.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 6-12, 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 6, 15 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the integrated circuit comprises an event queue configured to receive a plurality of event indices, the state machine being configured to read event indices on the event queue, wherein the reading by the state machine of an event index from the event queue causes the state machine to execute at least one of the plurality of functions (claim 6);
wherein the mapping interface comprises a communications interface for interfacing between a host system and the state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine (claim 15).
Response to Amendment
Applicant’s filing Terminal Disclaimer, see page 2, filed on April 29, 2026, with respect to the Double Patenting rejection has been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection is made in view of Chambers (‘994), Chambers (‘251).
Conclusion
Claims 1-5, 13-14 and 19-20 are rejected. Claims 6-12, 15-18 are objected
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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