DETAILED ACTION
The current Office Action is in response to the papers submitted 07/23/2024. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The claims disclose a first extraction circuit, a second extraction circuit, a command input buffer, a first command path, and a second command path. There is no mention of an extraction circuit, command path, command input buffer in the original specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first extraction circuit, second extraction circuit, command input buffer, first command path, and second command path must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show extracting at least one pulse a clock signal as described in the specification. The drawings shows a clock signal being sent to multiple devices that may select a specific clock signal but fails to show an actual extraction device or operation. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 discloses supplying pulses from clock signals to clock paths. The specification and drawings disclose that what is actually supplied to the clock paths is the output of logic gates 37 and 38 as shown in figures 3, 5, and 7. Logic gates 37 and 38 are AND gates as disclosed in paragraph 0014. The figured and specification disclose the block signal CK_E1 and CK_O1 are supplied to the AND gates 37 and 38. The outputs of AND gates 37 and 38 are what is supplied to the clock paths CK_E2 and CK_O2. The output of the AND gates 37 and 38 might match the clock signals CK_E1 or CK_O1 but the actual clock signals are not supplied to the clock paths. This shows the claims disclose a different function/system than what is disclosed in the original specification and claims.
Claims 10 - 14 disclose a first extraction circuit configured to extract at least one pulse from a first clock signal and a second extraction circuit configured to extract at least one pulse from a second clock signal. There is no mention in the original specification of an extraction circuit.
Claim 18 passing at least one pulse of a first clock signal and passing at least one pulse of a second clock signal based on when a first command is issued. The original drawings and specification disclose that a clock signal is used as a select for a latch to pass an input signal through the latch. The clock pulse is not what is passed but the input to the latch as disclosed in paragraph 0014. There is no mention of passing a pulse of a clock signal through anything in the original drawings or specification. The clock signals are used as control signals for latches or as input into AND logic gates. The output of the AND logic gate might match the input clock signal but it doesn’t “pass” a pulse of the clock signal. The output of the AND logic gate is a logical output based on the clock signal and another signal input into the AND logic gate.
Claim 18 discloses supplying the second command output from the first latch circuit to both the first and second command paths. The specification discloses the use of latches. However, the latches are disclosed as outputting data to only one device as shown in figures 2, 5, and 7. Latches 35 and 36 in figure 2 only have one output each that goes to a either 37 or 38 not both, latches 63 and 73 in figure 5 only have one output each that goes to either 64 or 74 not both, and latches 35 and 36 in figure 7 only have one output each that goes to a either 37 or 38 not both.
All remaining claims are rejected for being dependent on a rejected base claim.
Claims 1 - 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 discloses a second mode includes suppling the one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the first clock path and supply one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the second clock path. The specification and drawings show that clock paths CK_E2 and CK_O2 only carry one signal described and shown in the timing charts in figures 3 – 4, 6, and 8. This fails certain tests of the In Re Wands, 858 F.2d 731,737, 8USPQ2d 1400, 1404 tests of undue experimentation as listed and described below.
(A) Breadth Of The Claims:
The claims cover the idea of a clock path carrying pulse from multiple clock signals. The drawings and specification however show that each clock path carries a single signal at a time. The clock signals are also disclosed as having different phases meaning they have different values at the same time. Two different clock pulses cannot be supplied to a single clock path. This would require a level of combination or selection to supply the clock path with a single pulse value.
(B) The Nature Of The Invention:
The nature of the invention is adding more information to a data path then the data path can contain. The figures shows the clock path only contains a single bit value of information and the value is either high or low such as 1 or 0. There is no indication or explanation how a single clock path can contain two out of phase clock pulses. The clock pulses being out of phase would also indicate putting the two clock pulses on the same clock path would cancel each clock pulse out.
(C) The State Of The Prior Art:
The state of the prior art does not support the concept of putting two out of phase clock pulses onto the same clock path data line. One clock pulse can be supplied to the line at a time but not both. The clock path is discloses as containing a bit worth of information such as high or low as shown in the timing charts. Both clock pulses might be supplied to the multiplexors in the circuit diagrams. The selection input into the multiplexors only allows a single clock pulse to be supplied to the clock paths.
(D) The Level Of One Of Ordinary Skill:
One of ordinary skill would not understand or know how to supply a single clock path with two out of phase clock pulses when the clock path can only contain one clock pulse at a time. Supplying two out of phase clock pulses to a single data line would apparently cancel each other out also resulting in not signal being sent to the clock path.
(E) The Level Of Predictability In The Art:
It would not be expected that a clock path has contains a single bit worth of information, such as high and low, would be supplied from two different clock signals that each have a bit worth of information. This would require the clock path to contain two bits worth of information. It would also be predicted that since the clock pulses have different phases that the result would be no valid signal if they were combined to the single clock path since they would cancel each other out.
(F) The Amount Of Direction Provided By The Inventor:
The inventor has failed to provide adequate direction to explain how two different clock pulses with different phases can both be supplied to a single clock path data path where the clock path contains only one pulse value at a time. As shown by the drawings and support sections of the specification the multiplexors are supplied with two different clock signals. A selection input to the multiplexors directs the multiplexor to supply the clock path with only one clock signal at a time. There is no selection input to a multiplexor that would allow for a pulse from both clocks to be supplied to a clock path.
(G) The Existence Of Working Examples:
There is a lack of examples of two different signals being supplied to a single data path resulting in a single data value being shown on the data path.
(H) The Quantity Of Experimentation Needed To Make Or Use The Invention Based On The Content Of The Disclosure:
Due to the multiple issues listed above it would require an undo amount of experimentation to make and use the invention as claimed.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim 1 - 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 - 13 disclose a second mode includes suppling the one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the first clock path and supply one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the second clock path. As indicated above, the specification fails to sufficiently describe two different signals with different phases being supplied to a single data path resulting in a single data value being shown on the data path. The specification shows the multiplexors supplying only a single clock to the clock path at a time based on the selection signal sent to the multiplexors. This makes the limitation of a second mode suppling the one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the first clock path and supply one of the at least one pulse of the first clock signal and the at least one pulse of the second clock signal to the second clock path indefinite since it is unclear how the two pulses are supplied to the single clock path.
Claim 1 discloses first and second extraction circuits. There is no mention of extraction circuits in the specification or drawings. This shows the limitations of the extraction circuits are indefinite since they are not disclosed in specification.
Claim 2 discloses a command input buffer. There is no mention of a command input buffer in the specification or drawings. This shows the limitation of a command input buffer is indefinite since the command input buffer is not disclosed in the specification.
Claims 10 – 14 disclose a first extraction circuit and/or a second extraction circuit. There is no mention of an extraction circuit in the original specification. This makes the scope of what the extraction circuit is indefinite.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “extract” in claim 10 - 14 is used by the claim to mean “obtain” or “supply,” while the accepted meaning is “to pull or take out forcibly.” The clock signal is sent along data paths without force. The term is indefinite because the specification does not clearly redefine the term.
Claim 14 discloses a first extraction circuit, a second extraction circuit, a first multiplexor, and a second multiplexor. Paragraph 0020 discloses a pulse of a clock signal is extracted and supplied to a clock path via a multiplexor. This indicates the multiplexor is performing the extraction. The claims though indicate that the extraction circuits and multiplexors are different items. The disclosure in the specification makes it unclear and indefinite as to what are the extraction circuits and the multiplexors.
Claim 18 recites the limitation "the second command" in line 19. Multiple second commands are disclosed in lines 9, 14, and 16. It is unclear which second command the second command in line 19 refers back to. There is insufficient antecedent basis for this limitation in the claim. For examination the second command in line 19 will be treated as referring back to the second command in line 14.
Claims 19 – 20 are rejected for reciting the limitation “the second command” based on the same reasoning as claim 18.
All remaining claims are rejected for containing limitations rejected in a base claim and/or being dependent on a rejected base claim.
Examiner’s Note
Due to the numerous inconsistencies identified above between the current claims and original specification and drawings a proper scope of the claims cannot be determined at this time. The lack of any prior art rejections is not to be taken as any indication of patentability; it is a result of the indefiniteness of the scope of the invention. Specifically, it is unclear how to clock pulses are supplied to the clock path, what the extraction of a clock pulse entails, and what performs the extraction of the clock pulse. The Applicant is asked to make sure any future amendments to the claims put the claims in better form with regard to what is specifically disclosed in the original specification and drawings.
Conclusion
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2136