Office Action Predictor
Last updated: April 16, 2026
Application No. 18/781,233

METAL-PIEZOELECTRIC-METAL CAPACITOR

Non-Final OA §102§103
Filed
Jul 23, 2024
Examiner
OUTTEN, SAMUEL S
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., LTD.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
499 granted / 634 resolved
+10.7% vs TC avg
Strong +21% interview lift
Without
With
+20.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
668
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
48.6%
+8.6% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 634 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4 & 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Omura (US PGPub 20200212889). As per claim 1: Omura discloses in Figs. 6-7: An acoustic resonator comprising: a substrate (2); a piezoelectric layer (5) coupled to the substrate by one or more dielectric layers (42, [0033]) and having first and second surfaces that oppose each other; an interdigital transducer (IDT) (7A) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers; and a capacitor (C1, shown in related Fig. 9) electrically coupled in parallel to the IDT and including at least one first electrode (21) on the first surface of the piezoelectric layer and a metal layer (first portion 4121, [0066, 0072]) on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer. As per claim 2: Omura discloses in Figs. 6-7: the at least one first electrode is an anode of the capacitor and the metal layer is a cathode of the capacitor (the capacitor is a bi-directional circuit, such that either end may be considered the anode or cathode, but as per related Fig. 9, with the metal layer being towards ground, the metal layer provides the role of cathode). As per claim 3: Omura discloses in Figs. 6-7: the at least one first electrode comprises a pair of electrodes (first electrode 21 and second electrode 22) including an anode and a cathode of the capacitor. As per claim 4: Omura discloses in Figs. 6-7: the metal layer is a floating metal (portions 4121-4123 are floating, as seen in Figs. 6-7). As per claim 8: Omura discloses in Figs. 6-7: a Bragg mirror (first acoustic impedance layer 4A) disposed between the piezoelectric layer and the substrate. As per claim 9: Omura discloses in Figs. 6-7: the IDT comprises: a first busbar (71) and a second busbar (72) that each extend in a first direction from a first end to a second end thereof, a first plurality of electrode fingers extending from the first busbar in a second direction towards the second busbar, with the second direction intersecting the first direction, and a second plurality of electrode fingers extending from the second busbar in the second direction towards to the first busbar, such that the first and second plurality of electrode fingers form the interleaved fingers of the IDT (as seen in Fig. 6). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-5, 8-10, 13-15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dyer (US PGPub 20220247382) in view of Omura (US PGPub 20200212889). As per claim 1: Dyer discloses in Figs. 1, 5, & 8A: An acoustic resonator (X1, [0058-0059]) comprising: a substrate (120); a piezoelectric layer (110) coupled to the substrate by one or more dielectric layers (intermediate layers [0027] which may include a back side dielectric layer, [0033]) and having first and second surfaces (front and back [0033]) that oppose each other; an interdigital transducer (IDT) (130) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers (136); and a capacitor (C1) electrically coupled in parallel to the IDT and including at least one first electrode on the first surface of the piezoelectric layer (as seen in Fig. 8A, enlarged). Dyer does not disclose: including at least one first electrode on the first surface of the piezoelectric layer and a metal layer on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at least one first electrode (21) is on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7). At the time of filing, it would have been obvious to one of ordinary skill in the art to form the capacitor of Dyer using by sandwiching the piezoelectric layer between a first electrode on a first surface of the piezoelectric material and metal layer on a second side of the piezoelectric material as an alternative/equivalent capacitor able to provide the same function. As per claim 2: Dyer discloses in Figs. 1, 5, & 8A: The capacitor is a bi-directional circuit, such that either end may be considered to be the anode or the cathode. Dyer does not disclose: the at least one first electrode is an anode of the capacitor and the metal layer is a cathode of the capacitor. As a consequence of the combination of claim 1, the at least one first electrode is an anode of the capacitor and the metal layer is a cathode of the capacitor. As per claim 3: Dyer discloses in Figs. 1, 5, & 8A: Electrodes of the capacitor may each be connected to a separate bus bar of the IDT. Dyer does not disclose: the at least one first electrode comprises a pair of electrodes including an anode and a cathode of the capacitor. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at two first electrodes (21 & 22) are on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7), wherein the two first electrodes are at opposite ends of the circuit, forming an anode and a cathode. As a consequence of the combination of claim 1, the combination discloses the at least one first electrode comprises a pair of electrodes including an anode and a cathode of the capacitor. As per claim 4: Dyer does not disclose: the metal layer is a floating metal. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at two first electrodes (21 & 22) are on a first surface of a piezoelectric layer of the IDT and a floating metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7), wherein the two first electrodes are at opposite ends of the circuit, forming an anode and a cathode. As a consequence of the combination of claim 1, the combination discloses the metal layer is a floating metal. As per claim 5: Dyer discloses in Figs. 1, 5, & 8A: a portion of the piezoelectric layer forms a diaphragm that is over a cavity (845). Dyer further discloses that intermediate layers may be used to attach the piezoelectric layer to the substrate ([0027]). Dyer does not disclose that the cavity extends at least partially in the one or more dielectric layers. Omura discloses in Fig. 7: a substrate (2); a piezoelectric layer (5) coupled to the substrate by one or more dielectric layers (42, [0033]) and having first and second surfaces that oppose each other; and an interdigital transducer (IDT) (7A) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers. At the time of filing, it would have been obvious to one of ordinary skill in the art for the dielectric layer of Omura comprising the acoustic impedance layer (400) including the metal layer to be used as the intermediate layers of Dyer to provide the benefit of attaching the piezoelectric layer to the substrate as per Dyer, and also to provide the metal layer (4121-4122) of Omura to provide the alternative/equivalent capacitor of Omura. It would be further obvious to keep the cavity of Dyer in place of the acoustic impedance layer 4A of Omura, as cavities are art-recognized alternative/equivalent acoustic reflection structures to Bragg mirrors, as is well-understood in the art. As a consequence of the combination, the cavity extends at least partially in the one or more dielectric layers. As per claim 8: Dyer discloses in Figs. 1, 5, & 8A: intermediate layers may be used to attach the piezoelectric layer to the substrate ([0027]). Dyer does not disclose a Bragg mirror disposed between the piezoelectric layer and the substrate. Omura discloses in Fig. 7: a substrate (2); a piezoelectric layer (5) coupled to the substrate by one or more dielectric layers (42, [0033]) and having first and second surfaces that oppose each other; and an interdigital transducer (IDT) (7A) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers, wherein a Bragg mirror (first acoustic impedance layer 4A) is disposed between the piezoelectric layer and the substrate in the dielectric layers. At the time of filing, it would have been obvious to one of ordinary skill in the art for the dielectric layers of Omura comprising the acoustic impedance layers (400 & 4A) including the metal layer to be used as the intermediate layers of Dyer to provide the benefit of attaching the piezoelectric layer to the substrate as per Dyer, and also to provide the metal layer (4121-4122) of Omura to provide the alternative/equivalent capacitor of Omura. As a consequence of the combination, a Bragg mirror is disposed between the piezoelectric layer and the substrate. As per claim 9: Dyer discloses in Figs. 1, 5, & 8A: the IDT comprises: a first busbar and a second busbar (busbars 132 & 134) that each extend in a first direction from a first end to a second end thereof, a first plurality of electrode fingers extending from the first busbar in a second direction towards the second busbar, with the second direction intersecting the first direction, and a second plurality of electrode fingers extending from the second busbar in the second direction towards to the first busbar (fingers 136), such that the first and second plurality of electrode fingers form the interleaved fingers of the IDT (as seen in Fig. 1). As per claim 10: Dyer discloses in Figs. 1, 5, & 8A: the at least one first electrode includes: an anode of a capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of a capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers (Fig. 8A discloses the capacitor as being connected in parallel through connecting an anode and a cathode to the respective first and second busbars). Dyer does not disclose: the at least one first electrode includes: an anode of the capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of the capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at two first electrodes (21 & 22) are on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7), wherein the two first electrodes are at opposite ends of the circuit, forming an anode and a cathode. As a consequence of the combination of claim 1, the at least one first electrode includes: an anode of the capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of the capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers. As per claim 13: Dyer discloses in Figs. 1, 5, & 8A: A filter device (500) comprising: a plurality of bulk acoustic wave resonators (X1-X5, [0058-0059]), wherein at least one of the plurality of bulk acoustic wave resonators comprises: a substrate (120); a piezoelectric layer (110) coupled to the substrate by one or more dielectric layers (intermediate layers [0027] which may include a back side dielectric layer, [0033]) and having first and second surfaces (front and back [0033]) that oppose each other; an interdigital transducer (IDT) (130) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers (136); and a capacitor (C1) electrically coupled in parallel to the IDT and including at least one first electrode on the first surface of the piezoelectric layer (as seen in Fig. 8A, enlarged). Dyer does not disclose: including at least one first electrode on the first surface of the piezoelectric layer and a metal layer on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at least one first electrode (21) is on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7). At the time of filing, it would have been obvious to one of ordinary skill in the art to form the capacitor of Dyer using by sandwiching the piezoelectric layer between a first electrode on a first surface of the piezoelectric material and metal layer on a second side of the piezoelectric material as an alternative/equivalent capacitor able to provide the same function. As per claim 14: Dyer discloses in Figs. 1, 5, & 8A: The capacitor is a bi-directional circuit, such that either end may be considered to be the anode or the cathode. Dyer does not disclose: the at least one first electrode is an anode of the capacitor and the metal layer is a cathode of the capacitor. As a consequence of the combination of claim 13, the at least one first electrode is an anode of the capacitor and the metal layer is a cathode of the capacitor. As per claim 15: Dyer discloses in Figs. 1, 5, & 8A: Electrodes of the capacitor may each be connected to a separate bus bar of the IDT. Dyer does not disclose: the at least one first electrode comprises a pair of electrodes including an anode and a cathode of the capacitor, and the metal layer is a floating metal. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at two first electrodes (21 & 22) are on a first surface of a piezoelectric layer of the IDT and a floating metal layer (portions 4121-4123) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7), wherein the two first electrodes are at opposite ends of the circuit, forming an anode and a cathode. As a consequence of the combination of claim 13, the combination discloses the at least one first electrode comprises a pair of electrodes including an anode and a cathode of the capacitor, and the metal layer is a floating metal. As per claim 18: Dyer discloses in Figs. 1, 5, & 8A: the IDT of the at least one bulk acoustic wave resonator comprises: a first busbar and a second busbar (busbars 132 & 134) that each extend in a first direction from a first end to a second end thereof, a first plurality of electrode fingers extending from the first busbar in a second direction towards the second busbar, with the second direction intersecting the first direction, and a second plurality of electrode fingers extending from the second busbar in the second direction towards to the first busbar (fingers 136), such that the first and second plurality of electrode fingers form the interleaved fingers of the IDT (as seen in Fig. 1). As per claim 19: Dyer discloses in Figs. 1, 5, & 8A: the at least one first electrode includes: an anode of a capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of a capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers (Fig. 8A discloses the capacitor as being connected in parallel through connecting an anode and a cathode to the respective first and second busbars). Dyer does not disclose: the at least one first electrode includes: an anode of the capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of the capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at two first electrodes (21 & 22) are on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7), wherein the two first electrodes are at opposite ends of the circuit, forming an anode and a cathode. As a consequence of the combination of claim 13, the at least one first electrode includes: an anode of the capacitor that is coupled to the first busbar and extends in parallel to the first plurality of electrode fingers; and a cathode of the capacitor that is coupled to the second busbar and extends in parallel to the second plurality of electrode fingers. As per claim 20: Dyer discloses in Figs. 1, 5, & 8A: A radio frequency module comprising: A filter device (500) including a plurality of bulk acoustic wave resonators (X2 & X4, [0058-0059]) connected in parallel; and and a radio frequency circuit (filters are used in multiplexers, [0024], used in RF front-ends [0005] which inherently must have additional circuits connected to the filter to function) coupled to the filter device, the filter device and the radio frequency circuit being enclosed within a common package (a packaged device such as a telephone or laptop, [0005]), wherein at least one of the plurality of bulk acoustic wave resonators of the filter device includes: a substrate (120); a piezoelectric layer (110) coupled to the substrate by one or more dielectric layers (intermediate layers [0027] which may include a back side dielectric layer, [0033]) and having first and second surfaces (front and back [0033]) that oppose each other; an interdigital transducer (IDT) (130) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers (136); and a capacitor (C1) electrically coupled in parallel to the IDT and including at least one first electrode on the first surface of the piezoelectric layer (as seen in Fig. 8A, enlarged). Dyer does not disclose: including at least one first electrode on the first surface of the piezoelectric layer and a metal layer on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer. Omura discloses in Figs. 6 & 7: An alternative capacitor that can be connected in parallel to an IDT (7A) wherein at least one first electrode (21) is on a first surface of a piezoelectric layer of the IDT and a metal layer (portion 4121) is on the second surface of the piezoelectric layer, such that the piezoelectric layer is sandwiched between the at least one first electrode and the metal layer (as seen in Fig. 7). At the time of filing, it would have been obvious to one of ordinary skill in the art to form the capacitor of Dyer using by sandwiching the piezoelectric layer between a first electrode on a first surface of the piezoelectric material and metal layer on a second side of the piezoelectric material as an alternative/equivalent capacitor able to provide the same function. Or in the alternative, Dyer does not disclose a radio frequency circuit coupled to the filter device, the filter device and the radio frequency circuit being enclosed within a common package. At the time of filing, it would have been obvious to one of ordinary skill in the art to connect the filter to an additional radio frequency circuit such as an additional filter in a multiplexer and for the filters to be enclosed in a common package to provide the benefit of functionality as part of an RF-front end in a device that further provides the benefit of minimizing the size of the circuitry, as is well understood in the art. Claim(s) 6-7, 11, & 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the resultant combination of r Dyer (US PGPub 20220247382) in view of Omura (US PGPub 20200212889) as applied to claims 1, 5, & 13 above, and further in view of Kando et al. (US PGPub 20140152145) As per claims 1, 5, & 13, the resultant combination discloses the acoustic resonator and filter device as rejected above. As per claim 6: The resultant combination does not disclose the IDT is disposed on the second surface of the piezoelectric layer that faces the cavity. Kando et al. discloses in Figs. 3A & 3B: An IDT (5) may be located on a top surface of a piezoelectric layer (4) facing away from a cavity (recess 2a) or a bottom surface facing towards a cavity. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the IDT of the resultant combination on the second surface of the piezoelectric layer that faces the cavity, as one of a limited number of equivalent options shown as two alternative/equivalent possibilities by Kando et al. (Fig. 3A-3B) As per claim 7: The resultant combination discloses in Dyer, Figs. 1, 5, & 8A: the IDT is configured such that a radio frequency signal applied to the IDT excites a bulk shear acoustic wave in the diaphragm ([0010]) where acoustic energy propagates along a direction substantially orthogonal to a surface of the piezoelectric layer, which is transverse to a direction of an electric field created by the interleaved fingers of the IDT. As per claim 11: The resultant combination discloses in Dyer, that the cavity may be a recess formed in the substrate through selective etching after the piezoelectric substrate is attached ([0028]) The resultant combination does not disclose: the piezoelectric layer comprises a pair of through holes that extend along sides of the at least one first electrode of the capacitor in a thickness direction of the piezoelectric layer. Kando et al. discloses in Fig. 1A-B: The use of selective etching to form a recess 2a below a piezoelectric membrane through the use of openings (6 & 7) alongside the IDT ([0181]). At the time of filing, it would have been obvious to one of ordinary skill in the art for the cavity of the resultant combination to be formed as per the method of Kando, such that a pair of through holes is formed in the piezoelectric layer in the thickness direction that extend along sides of the IDT over the cavity, and thus extending along sides of the at least one first electrode of the capacitor in a thickness direction of the piezoelectric layer. As per claim 16: The resultant combination discloses in Dyer that a portion of the piezoelectric layer forms a diaphragm that is over a cavity (838), and further discloses that intermediate layers may be used to attach the piezoelectric layer to the substrate ([0027]). The resultant combination does not disclose that the cavity extends at least partially in the one or more dielectric layers, and the IDT is disposed on the second surface of the piezoelectric layer that faces the cavity. Omura discloses in Fig. 7: a substrate (2); a piezoelectric layer (5) coupled to the substrate by one or more dielectric layers (42, [0033]) and having first and second surfaces that oppose each other; and an interdigital transducer (IDT) (7A) on at least one of the first and second surfaces of the piezoelectric layer and including interleaved fingers. Kando et al. discloses in Figs. 3A & 3B: An IDT (5) may be located on a top surface of a piezoelectric layer (4) facing away from a cavity (recess 2a) or a bottom surface facing towards a cavity. At the time of filing, it would have been obvious to one of ordinary skill in the art for the dielectric layer of Omura comprising the acoustic impedance layer (400) including the metal layer to be used as the intermediate layers of Dyer to provide the benefit of attaching the piezoelectric layer to the substrate as per Dyer, and also to provide the metal layer (4121-4122) of Omura to provide the alternative/equivalent capacitor of Omura. It would be further obvious to keep the cavity of Dyer in place of the acoustic impedance layer 4A of Omura, as cavities are art-recognized alternative/equivalent acoustic reflection structures to Bragg mirrors, as is well-understood in the art. It would have been further obvious to one of ordinary skill in the art to form the IDT of the resultant combination on the second surface of the piezoelectric layer that faces the cavity, as one of a limited number of equivalent options shown as two alternative/equivalent possibilities by Kando et al. (Fig. 3A-3B) As a consequence of the combination, the cavity extends at least partially in the one or more dielectric layers, and the IDT is disposed on the second surface of the piezoelectric layer that faces the cavity. As per claim 17: The resultant combination discloses in Dyer, Figs. 1, 5, & 8A: the IDT is configured such that a radio frequency signal applied to the IDT excites a bulk shear acoustic wave in the diaphragm ([0010]) where acoustic energy propagates along a direction substantially orthogonal to a surface of the piezoelectric layer, which is transverse to a direction of an electric field created by the interleaved fingers of the IDT. Allowable Subject Matter Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: claim 12 was not disclosed or rendered obvious over the closest found prior art of Omura and Dyer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL S OUTTEN whose telephone number is (571)270-7123. The examiner can normally be reached M-F: 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Samuel S Outten/Primary Examiner, Art Unit 2843
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Prosecution Timeline

Jul 23, 2024
Application Filed
Dec 06, 2025
Non-Final Rejection — §102, §103
Mar 30, 2026
Response Filed

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Expected OA Rounds
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