DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 07/23/24 for application number 18/781,289. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, Claims, and Certified Copy of Foreign Priority Application.
The Preliminary Amendment filed 08/29/24 is acknowledged. Claims 1-20 are cancelled, and Claims 21-40 are added. Claims 21-40 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 21, 26, 31, 32, 33, 36, 37, 39, and 40 are objected to because of the following informalities:
Claim 21, line 3 recites, “a plurality of memories” (emphasis added) and should instead read, “a plurality of memory chips” (emphasis added) to clarify physical memory chips as recited in the Specification.
Claims 26, 31, 32, 33, 36, 37, 39, and 40 recite similar instances of “memories” and are objected to accordingly.
Claim 21, line 8 recites, “receive an address for the plurality of memories through the plurality of input/output pins” (emphasis added) and should instead read, “receive an address for each of the plurality of memory chips through the plurality of input/output pins” (emphasis added) Appropriate correction is required.
Allowable Subject Matter
Claims 24, 27-31, 36, and 38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23, 25, 32-35, 39, and 40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al., US 2018/0350414 A1 (as cited in the IDS 07/23/24).
Regarding Claim 21, Park discloses a memory device [system of Fig. 13] comprising:
a clock pin [301];
a plurality of memories connected to the clock pin [memory chips (MC) 100, 200, 300 all connected via their respective nodes to buffer chip 400, which is connected to clock pin 301]; and
a plurality of input/output pins commonly connected to the plurality of memories, wherein the memory device is configured to:
receive a duty correction circuit (DCC) command through the plurality of input/output pins in a first period of a DCC training period [write data indicating a start of a duty correction operation may be transmitted in the first period PR1; transmission is through SL3, a data line (which is connected via pins), par 77];
receive an address for the plurality of memories through the plurality of input/output pins in a second period of the DCC training period [in the second period PR2, a random read command RR and the address ADDR may be applied, e.g. sequentially applied, through the data line (which is connected via pins), par 78]; and
receive a clock signal through the clock pin in a third period of the DCC training period, and wherein the plurality of memories is configured to perform duty correction operations on a plurality of internal clock signals generated based on the clock signal during the third period of the DCC training period [In the third period PR3, a second set feature command SF2 and the address ADDR may be applied, e.g. sequentially applied, through the data line, and then the write data WD indicating an end of the duty correction operation may be applied. By the write data WD applied in the third period PR3, the operating features of the nonvolatile memory may be corrected to the normal operation from the duty correction sequence; i.e. duty correction is performed in the third period; correction being of the clocks of the respective memories (i.e. internal clock signals).
Regarding Claim 22, Park discloses the memory device of Claim 21, wherein the DCC command includes a set feature command or a DCC training command [in the first period PR1, a first set feature command SF1 and an address ADDR may be applied, par 77].
Regarding Claim 23, Park discloses the memory device of Claim 21, wherein the clock signal includes a read enable signal [clock signal during duty correction sequence may be a read enable signal, par 82].
Regarding Claim 25, Park discloses the memory device of Claim 21, wherein the duty correction operations are performed in parallel during the third period of the DCC training period [duty correction takes place in third period PR3; in a DCC training period, the DCCs 120 and 220 may perform a duty correction operation in parallel on an internal clock signal based on the buffered clock signal CLKb, par 79, 87].
Regarding Claim 32, Park discloses memory device of Claim 21, wherein the plurality of memories includes a plurality of memory chips [memories MC1-MC3 are memory chips, Fig. 13].
Regarding Claim 33, Park discloses a controller [within memory 30A, Fig. 13]. The remainder of Claim 33 recites limitations similar to those of Claim 21, and is rejected accordingly.
Regarding Claim 34, 35, and 39, Park discloses the controller of Claim 33. Claims 34, 35, and 39 recite limitations similar to those of Claims 22, 23, and 32, respectively, and are rejected accordingly.
Regarding Claim 40, Park discloses a memory device [30A, Fig. 13]. The remainder of Claim 40 recites limitations similar to those of Claim 21, and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 26 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Brox et al., US 2020/0312399 A1.
Regarding Claim 26, Park discloses the memory device of Claim 21. While Park discloses the plurality of input/output pins includes a first pin, a second pin, a third pin, and a fourth pin, and wherein the plurality of memories comprises: a first memory and a second memory [memory chips MC1-MC3 with nodes ND11-ND32 acting as pins for the respective memory chips, Fig. 13], Park does not explicitly teach generating a first signal by adjusting a duty cycle of a first internal clock signal of the plurality of internal clock signals based on a first comparison signal received from the second pin, and output the first signal through the first pin; and generating a second signal by adjusting a duty cycle of a second internal clock signal of the plurality of internal clock signals based on a second comparison signal received from the fourth pin, and output the second signal through the third pin.
In the analogous art of clock correction, Brox teaches generating a first signal by adjusting a duty cycle of a first internal clock signal of the plurality of internal clock signals based on a first comparison signal received from the second pin, and output the first signal through the first pin; and generating a second signal by adjusting a duty cycle of a second internal clock signal of the plurality of internal clock signals based on a second comparison signal received from the fourth pin, and output the second signal through the third pin [Clock signal from DCC 510 that goes to clock divider to send clock 0 and 180 to DCC 520-a, and then DCC controller 525-a compares the two clocks to send a signal back to DCC 520-a, with a parallel process occurring for the Clock’ signal and DCC 520-b with DCC controller 525-b, Fig. 5].
It would have been obvious to one of ordinary skill in the art, having the teachings of Park and Brox before him before the effective filing date of the claimed invention, to incorporate the adjustment as taught by Brox into the device as disclosed by Park, to allow for memory devices to use multiple clock signals to convey timing information for various operations [Brox, par 4].
Regarding Claim 37, Park discloses the controller of Claim 33. Claim 37 recites limitations similar to those of Claim 26, and is rejected accordingly.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175