Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 12 and 16.
b. Claims 1-20 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 01/23/2026. The changes and remarks disclosed therein were considered.
Claims 1, 2, 12, 13, 16 and 17 has been amendment. Therefore, claims 1-20 are pending in the application.
Drawings
3. The drawings were received on 07/23/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 11/11/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/19/2024. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 07/26/2024. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-3, 12 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bai et al (Patent No.: US 10,839,897 B1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Bai et al in Figures 1-7 are directly discloses a memory device (a memory system 101, Fig. 1A) comprising:
a three-dimensional array (a three dimensional array 416) of nodes configured on a semiconductive substrate (a global bitline 1-2, GBL1, GBL2, Fig. 4B), each respectively node in the array having:
a selector transistor (a select transistor Q11….Q13, Fig. 4B); and
a memory cell (a plurality of memory cells M111…..M236, Fig. 4A) having:
a first layer (a first memory level 412, Fig. 4A) of conductive material configured as a first electrode terminal of the memory cell, the first electrode terminal connected to the selector transistor (the select transistor Q11)(the memory level 412 such as memory cell M111 coupled to the wordline WL10, the bitline LBL11 coupled to the source of select transistor Q11 and the row select line SG1 coupled to the gate of select transistor Q11, Fig. 4A);
Regarding dependent claim 2, Bai et al in Figures 1-7 are directly discloses a memory device (a memory system 101, Fig. 1A) comprising: wherein the memory cell further comprises:
a second layer (a second memory level 410, Fig. 4A) of conductive material configured as a second electrode terminal of the memory cell (a plurality of memory cells M111…..M236, Fig. 4A) (the memory level 410 such as memory cell M211 coupled to the wordline WL20, the bitline LBL11 coupled to the source of select transistor Q11 and the row select line SG1 coupled to the gate of select transistor Q11, Fig. 4A); and
a layer of a chalcogenide alloy (a memory material 414 such as chalcogenide material, Fig. 4b, column 11, lines 40-52) sandwiched between the first electrode terminal and the second electrode terminal and wherein the chalcogenide alloy includes a ternary Indium-Arsenic-Selenium material (the chalcogenide material composed primary of element picked from such as Ge, Se, As, Te Sb, Si, C205 and N material)(the memory material 414 such as the phase change includes the chalcogenide material disposed in vertical strips of a nonvolatile memory material, see at in Figures 1 and 4, column 4, lines 43 to column 8, lines 36 and column 10, lines 53 to column 12, lines 2 and the related disclosures).
Regarding dependent claim 3, Bai et al in Figures 1-7 are directly discloses a memory device (a memory system 101, Fig. 1A) comprising: wherein the memory cell further comprises: wherein the chalcogenide alloy includes a ternary Indium-Arsenic-Tellurium material (the chalcogenide material composed primary of element picked from such as Ge, Se, As, Te Sb, Si, C205 and N material).
Regarding to independent claim 12, Bai et al in Figures 1-7 are directly discloses an apparatus (a memory system 101, Fig. 1A) comprising:
a controller (a memory chip controller 105, Fig. 1A);
bitline drivers (a local bit line LBL11….LBL33, Fig. 4A) controlled by the controller (the memory chip controller 105);
wordline drivers (a global wordline WL10….WL20, Fig. 4A) controlled by the controller (the memory chip controller 105);
digit line drivers (a row select line SG1…SG3, Fig. 4A) controlled by the controller (the memory chip controller 105); and
a three-dimensional array (a three dimensional array 416) of nodes configured on a semiconductive substrate (a global bitline 1-2, GBL1, GBL2, Fig. 4B), a node in the array having: a selector transistor (a select transistor Q11….Q13, Fig. 4B); and
a memory cell (a plurality of memory cells M111…..M236, Fig. 4A) having:
a first layer (a first memory level 412, Fig. 4A) of conductive material configured as a first electrode terminal of the memory cell, the first electrode terminal connected to the selector transistor (the select transistor Q11)(the memory level 412 such as memory cell M111 coupled to the wordline WL10, the bitline LBL11 coupled to the source of select transistor Q11 and the row select line SG1 coupled to the gate of select transistor Q11, Fig. 4A);
a second layer (a second memory level 410, Fig. 4A) of conductive material configured as a second electrode terminal of the memory cell (a plurality of memory cells M111…..M236, Fig. 4A) (the memory level 410 such as memory cell M211 coupled to the wordline WL20, the bitline LBL11 coupled to the source of select transistor Q11 and the row select line SG1 coupled to the gate of select transistor Q11, Fig. 4A); and
a layer of a chalcogenide alloy (a memory material 414 such as chalcogenide material, Fig. 4b, column 11, lines 40-52) sandwiched between the first electrode terminal and the second electrode terminal (the memory material 414 such as the phase change includes the chalcogenide material disposed in vertical strips of a nonvolatile memory material, see at in Figures 1 and 4, column 4, lines 43 to column 8, lines 36 and column 10, lines 53 to column 12, lines 2 and the related disclosures).
Regarding claim 16, they encompass the same scope of invention as that of claims 1-3 and 12, except they draft the invention in method format instead of apparatus format. Bai et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claim 16, is therefore rejected in method format for the same reasons claims 1-3 and 12, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 4-11, 13-15 and 17-20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 4-11, the prior art fails to tech or suggest the claimed limitations, namely, the memory cell is programmable to have a polarity induced threshold window, wherein the memory cell is programmable, via a current lower than 50 mA to have the polarity induced threshold window, wherein the chalcogenide alloy is deposited via a technique of atomic layer deposition, wherein the chalcogenide alloy is deposited via a technique of physical vapor deposition, wherein the three-dimensional array of nodes include: first nodes stacked in a first direction; and second nodes stacked in the first direction and configured next to the first nodes in a slice of nodes extending in the first direction and a second direction; wherein the memory device includes a conductive pillar extending in the first direction and configured between the first nodes and the second nodes; and wherein each of the first nodes and the second nodes has an electrode terminal connected to the conductive pillar.
With respected to dependent claims 13-15, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: a digit line connected to one of the digit line drivers; and a thin film transistor having a source-drain channel and a gate; wherein a gate of the selector transistor is connected to one of the bitline drivers; wherein the second electrode terminal of the memory cell is connected via the source-drain channel of the thin film transistor to the digit line; wherein the gate of the thin film transistor is connected to one of the wordline drivers; and wherein the chalcogenide alloy includes a ternary Indium-Arsenic-Selenium material or a ternary Indium-Arsenic-Tellurium material, deposited via a technique of atomic layer deposition.
With respected to dependent claims 17-20, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: selecting the memory cell by controlling the bitline driver to drive a voltage to turn on the selector transistor, and controlling the wordline driver to drive a voltage to turn on the thin film transistor, further comprising: programming the memory cell to have a polarity induced threshold window by controlling the digit line driver to cause a current lower than 50 *** ERROR: No Symbol mapping for puaHex=6D. Looks like μ may have been intended. ***A, to flow through the memory cell.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishihara et al (US. 7,781,807 B2) discloses a three-dimensional semiconductor storage device.
Gomes et al (US. 2022/0308995 A1) discloses integrated three-dimensional dram cache.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov