DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over in view of
Male et al. (US 20200168530) in view of Vishwanath et al. (US 11088699).
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With respect to claim 1, Male et al. (US 20200168530). discloses a semiconductor device comprising: a lead frame ([0020]”leadframe including a die pad 105 and leads 106 around the die pad 105 ”); a first semiconductor chip (120’) mounted face-up above the lead frame; and a second semiconductor chip (110’) mounted face-down above the first semiconductor chip (120’), the second semiconductor chip having a chip size smaller than a chip size of the first semiconductor chip, wherein the second semiconductor chip includes a bandgap element (310) including a positive-negative (PN) junction and included in a band gap reference circuit (110’), but fails to disclose the band gap reference circuit included in the second semiconductor chip receives a DC voltage as an input to output a reference voltage, and the second semiconductor chip includes: an input terminal through which trimming information is input, the trimming information being for adjusting the reference voltage output by the band gap reference circuit; and a storage circuit (memory) that holds the trimming information.
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Vishwanath et al. discloses a band gap circuit for use in a (ADC or DAC) having a trimming function and a memory (e.g., see Col. 6 lines 30-31; there's also additional trim control registers in the other trim devices) the band gap reference circuit included in a semiconductor chip receiving a DC voltage (VDD) as an input (at Vin) to output a reference voltage (VBG) , and the semiconductor chip includes: an input terminal through which trimming information is input, the trimming information being for adjusting the reference voltage output (at 110) by the band gap reference circuit; and a storage circuit (memory, see Col. 6 lines 30-31; there's also additional trim control registers in the other trim devices)) that holds the trimming information.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the circuit in Vishwanath et al. as the reference voltage in Male et al. for the purpose of providing details to voltage reference circuit of 315a in Male et al.
Allowable Subject Matter
Claim 2 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, Male discloses the semiconductor device according to claim 1, wherein the first semiconductor chip supplies the DC voltage to the second semiconductor chip, and the second semiconductor chip supplies the reference voltage to the first semiconductor chip.
Here, claim 2 requires that the first chip supplies the DC voltage to the second semiconductor chip. Wherein due to the second interpretation the only voltage 120" receives is the reference voltage VREF. The DC voltage, e.g., VDD/power supply voltage is not directly provided to 120' via 110, only the reference voltage VREF
Claims 4-10 and 12 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 4, the prior art fails to suggest or disclose the semiconductor device according to claim 2, wherein the first semiconductor chip and the second semiconductor chip include a clock terminal as a terminal connecting each other, the clock terminal being for supplying a clock signal from the first semiconductor chip to the second semiconductor chip, and the band gap reference circuit includes: a plurality of devices for use in outputting the reference voltage; and a selection circuit that periodically switches a combination of devices to be used among the plurality of devices according to the clock signal.
With respect to claim 9, the prior art fails to suggest or disclose the semiconductor device according to claim 2, wherein the first semiconductor chip includes a secondary band gap reference circuit.
With respect to claim 12, the prior art fails to suggest or disclose the semiconductor device according to claim 2, wherein the second semiconductor chip has a dielectric isolation structure.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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