DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 08/17/2026 Amendment and RCE.
Claims 1, 3-11 and 14-19 are pending and examined. Claims 2, 12-13, and 20 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,204,692 to Kamata et al. (hereafter Kamata) in view of US 10,895,999 to Hsiao (hereafter Hsiao) in view of US 11,393,533 to Zhan et al. (hereafter Zhan).
Regarding independent claim 1, Kamata teaches an apparatus, comprising:
an array of memory cells (FIG. 1: memory cell array 11); and
a controller coupled to the array of memory cells (FIG. 1: logic controller 16), wherein the controller is configured to:
apply a pass voltage to a wordline in the array of memory cells (FIG. 12: applying Vread to selected WL from t0-t1);
apply a read voltage to the wordline (FIG. 12: applying AR to selected WL from t1-t3);
apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline FIG. 12: applying CR+CGkick to selected WL right at t3, wherein the magnitude of CGkick can be set to any numerical value, see 13:37-48); and
Annotated FIG. 12
PNG
media_image1.png
593
527
media_image1.png
Greyscale
Kamata does not teach the strikethrough limitations. However, Kamata further describes that ramp-up and ramp-down time depends on RC constant. FIG. 12 depicts a solid line and a dashed line corresponding to voltage waveforms associated with a near-side word line and a far-side word line of a memory array, respectively. Because the near-side word line has a lower RC constant, its voltage ramp-up and ramp-down times are shorter compared to those of the far-side word line, which has a higher RC constant.
Hsiao teaches initiating a read recovery by applying a second read voltage higher than a first read voltage in response to the number of errors exceeding a threshold number of errors (FIG. 7B: applying V(2)6 higher than V(1)6 to obtain soft information for error correction, see 12:45-13:21, when the number of errors is greater than number of correctable errors, see 3:46-62 and 13:65-14:14).
Zhan teaches wherein the controller is configured to change trim settings (trim value associated with RC constant on lookup table, see 10:55-11:9) to implicitly increase precharge time (because RC constant is a function of initial voltage value, final stable voltage value, and discharge time, see 2:53-64. As the result, precharge time and discharge time are also a function of RC constant, initial voltage value, and final stable voltage value. It is understood that the higher than final stable voltage value, the longer the ramp-up and ramp-down time with no change in RC constant and initial voltage value).
Since Kamata, Hsiao and Zhan are all from the same field of endeavor, the purpose disclosed by Hsiao and Zhan would have been recognized in the pertinent art of Kamata.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
initiate a read recovery as suggested by Hsiao to the memory array of Kamata as needed in order to maintain the integrity of the memory array.
realize that, voltage V(2)6 of Hsiao is higher than voltage V(1)6 during a read recovery. Applying that to Kamata, voltage V(2)6 + CGkick of Kamata would also be higher than voltage V(1)6 + CGkick during a read recovery. Therefore, the wordline of Kamta will take longer ramp-up time to voltage V(2)6 + CGkick and longer ramp-down time from voltage V(2)6 + CGkick compared to voltage V(1)6 + CGkick as Zhan describes.
Regarding dependent claim 3, Hsiao teaches wherein the read recovery includes at least one of a read retry, a soft bit read, or a corrective read (i.e. soft bit read to obtain soft information for error correction, see 12:45-13:21).
Regarding dependent claim 4, Hsiao teaches wherein the wordline includes triple level cells (TLCs) (see 11:30-47).
Regarding dependent claim 5, Hsiao does not explicitly teach wherein the controller is configured to increase a read window budget by greater than 50 mV in response to applying the read voltage overdrive to TLCs. However, it would have been obvious to one with ordinary skill in the art to realize that value for increase a read window budget is often a design choice depending on the type of memory device.
Regarding dependent claim 6, Hsiao teaches wherein the wordline includes quad-level cells (QLCs) (see 11:30-47).
Regarding dependent claim 7, Hsiao does not explicitly teach wherein the controller is configured to increase a read window budget by greater than 190 mV in response to applying the read voltage overdrive to QLCs. However, it would have been obvious to one with ordinary skill in the art to realize that value for increasing a read window budget is often a design choice depending on the type of memory device.
Regarding independent claim 8, Kamata teaches an apparatus, comprising:
an array of non-volatile memory cells (FIG. 1: memory cell array 11); and
a controller coupled to the array of non-volatile memory cells (FIG. 1: logic controller 16), wherein the controller is configured to:
apply a read voltage to a wordline in the array of non-volatile memory cells (FIG. 12: applying Vread to selected WL from t0-t1);
;
apply a read voltage overdrive to the wordline greater than the read voltage (FIG. 12: applying CR+CGkick to selected WL right at t3, wherein the magnitude of CGkick can be set to any numerical value, see 13:37-48)
Kamata does not teach the strikethrough limitations. However, Kamata further describes that ramp-up and ramp-down time depends on RC constant. FIG. 12 depicts a solid line and a dashed line corresponding to voltage waveforms associated with a near-side word line and a far-side word line of a memory array, respectively. Because the near-side word line has a lower RC constant, its voltage ramp-up and ramp-down times are shorter compared to those of the far-side word line, which has a higher RC constant.
Hsiao teaches initiating a read recovery by applying a second read voltage higher than a first read voltage in response to the number of errors exceeding a threshold number of errors (FIG. 7B: applying V(2)6 higher than V(1)6 to obtain soft information for error correction, see 12:45-13:21, when the number of errors is greater than number of correctable errors, see 3:46-62 and 13:65-14:14), wherein V(2)6 highest read voltage applied to the wordline during a read recovery (FIG. 7B: V(2)6 higher than V(1)6).
Zhan teaches wherein the controller is configured to change trim settings (trim value associated with RC constant on lookup table, see 10:55-11:9) to implicitly increase precharge time (because RC constant is a function of initial voltage value, final stable voltage value, and discharge time, see 2:53-64. As the result, precharge time and discharge time are also a function of RC constant, initial voltage value, and final stable voltage value. It is understood that the higher than final stable voltage value, the longer the ramp-up and ramp-down time with no change in RC constant and initial voltage value).
Since Kamata, Hsiao and Zhan are all from the same field of endeavor, the purpose disclosed by Hsiao and Zhan would have been recognized in the pertinent art of Kamata.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
initiate a read recovery as suggested by Hsiao to the memory array of Kamata as needed in order to maintain the integrity of the memory array.
realize that, voltage V(2)6 of Hsiao is higher than voltage V(1)6 during a read recovery. Applying that to Kamata, voltage V(2)6 + CGkick of Kamata would also be higher than voltage V(1)6 + CGkick during a read recovery. Therefore, the wordline of Kamta will take longer ramp-up time to voltage V(2)6 + CGkick and longer ramp-down time from voltage V(2)6 + CGkick compared to voltage V(1)6 + CGkick as Zhan describes.
Regarding dependent claim 9, Hsiao teaches wherein the apparatus is a three-dimensional NAND (3D NAND) device (see 11:30-47).
Regarding dependent claim 10-11, Hsiao does explicitly teach wherein the 3D NAND device includes polysilicon (poly) channel traps. However, it would have been obvious to one with ordinary skill in the art to realize that polysilicon is commonly used as channel material in 3D NAND device ), and the applied read voltage causes detrapping of electrons in the poly channel traps.
Regarding dependent claims 14-15, Zhan does not explicitly teach wherein the precharge time is greater than 2 microseconds in response to the wordline including triple level cells (TLCs), and wherein the precharge time is greater than 5 microseconds in response to the wordline including quad-level cells (QLCs). However, it would have been obvious to one with ordinary skill in the art to realize that value for increase precharge time is often a design choice depending on the type of memory device.
Regarding independent claim 16, Kamata teaches a method, comprising:
applying a pass voltage to a wordline in an array of memory cells (FIG. 12: applying Vread to selected WL from t0-t1);
applying a first read voltage to the wordline (FIG. 12: applying AR to selected WL from t1-t3);
applying a read voltage overdrive greater than the first read voltage and equal to the pass voltage to the wordline FIG. 12: applying CR+CGkick to selected WL right at t3, wherein the magnitude of CGkick can be set to any numerical value, see 13:37-48. This implies CR+CGkick can be set equal to Vread);
Kamata does not teach the strikethrough limitations. However, Kamata further describes that ramp-up and ramp-down time depends on RC constant. FIG. 12 depicts a solid line and a dashed line corresponding to voltage waveforms associated with a near-side word line and a far-side word line of a memory array, respectively. Because the near-side word line has a lower RC constant, its voltage ramp-up and ramp-down times are shorter compared to those of the far-side word line, which has a higher RC constant.
Hsiao teaches initiating a read recovery by applying a second read voltage higher than a first read voltage in response to the number of errors exceeding a threshold number of errors (FIG. 7B: applying V(2)6 higher than V(1)6 to obtain soft information for error correction, see 12:45-13:21, when the number of errors is greater than number of correctable errors, see 3:46-62 and 13:65-14:14).
Zhan teaches wherein the controller is configured to change trim settings (trim value associated with RC constant on lookup table, see 10:55-11:9) to implicitly increase precharge time (because RC constant is a function of initial voltage value, final stable voltage value, and discharge time, see 2:53-64. As the result, precharge time and discharge time are also a function of RC constant, initial voltage value, and final stable voltage value. It is understood that the higher than final stable voltage value, the longer the ramp-up and ramp-down time with no change in RC constant and initial voltage value).
Since Kamata, Hsiao and Zhan are all from the same field of endeavor, the purpose disclosed by Hsiao and Zhan would have been recognized in the pertinent art of Kamata.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
initiate a read recovery as suggested by Hsiao to the memory array of Kamata as needed in order to maintain the integrity of the memory array.
realize that, voltage V(2)6 of Hsiao is higher than voltage V(1)6 during a read recovery. Applying that to Kamata, voltage V(2)6 + CGkick of Kamata would also be higher than voltage V(1)6 + CGkick during a read recovery. Therefore, the wordline of Kamta will take longer ramp-up time to voltage V(2)6 + CGkick and longer ramp-down time from voltage V(2)6 + CGkick compared to voltage V(1)6 + CGkick as Zhan describes.
Regarding dependent claims 17-19, Kamata does not explicitly describe the recited features. However, there are similarity in applying voltages to selected word line between Kamata and FIG. 4 of the present invention.
It would have been obvious to one with ordinary skill in the art to realize that a recitation of the intended use of the claimed invention must result in a method difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art method is capable of performing the intended use, then it meets the claim. MPEP § 2114.
Response to Arguments
Applicant's arguments filed 08/17/2026 have been fully considered but they are not persuasive.
Examiner kindly refers Applicant to above rejections for details.
Claims 1, 3-11 and 14-19 maintain rejected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
September 23, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
