Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 07/23/2024. Claims 1-20 are pending on this application.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The subject matter “a bandpass of the low pass filter” in the claimed as being indefinite for failing to particularly point out and distinctly claim the subject matter of the claimed invention, because a low-pass filter is not a bandpass filter. A low-pass filter allows only frequencies below a cutoff point to pass, attenuating high frequencies. Conversely, a bandpass filter passes only a specific range of frequencies between a lower and upper cutoff, attenuating both low and high frequencies. Therefore, the subject matter “a bandpass of the low pass filter” does distinctly for a lowpass filter or a bandpass filter as claimed.
5. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The claim contains the subject matter “an order of magnitude lower than a DAC update rate” which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention; because Magnitude is measures absolute value, or amount of energy released, while rate is measuring the speed of change over time. Magnitude represents "how much" whereas rate represents "how fast"; thus, there is no higher or lower between magnitude and rate. Accordingly, claim 19 contains the subject matter “an order of magnitude lower than a DAC update rate” which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lazarov et al. Pub. No. 2019/0041471 in view of Huang et al. Pub. No. 2008/0024338.
Regarding claim 1. Fig. 2 of Lazarov et al. discloses a method of generating of an adjusted output signal (output of Corrected ADC result) , the method comprising: providing an unadjusted voltage reference (ADC Vref 204) ; receiving at least one of a first calibrated voltage (VCAL_PNP) based on a base-emitter voltage of one or more pnp transistors (paragraph 0026 discloses “Vptat may be based on the base-emitter voltage of the one or more pnp transistors of calibration circuit 208”), a second calibrated voltage (VCAL_NPN) based on a base-emitter voltage of one or more npn transistors (paragraph 0026 discloses “Vptat may be based on the base-emitter voltage of the one or more pnp transistors of calibration circuit 208”), and a voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026), determining (ADC 202) a digital estimate (digital Vout of ADC 202) of the output signal (output of Corrected ADC result) based on an analog (analog Vin) representation of the output signal (Corrected ADC result), and based on the at least one of the first calibrated voltage (VCAL_PNP), the second calibrated voltage (VCAL_NPN), and the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026); deriving an error (paragraph 0025 discloses “gain correction factor G is calculated to bring the error in the measurement of sense voltage Vsns_n to zero”) based on a difference (paragraph 0057 discloses “digital gain correction is determines to scaled the non-ideal ADC output codeADC: G=VREF/VREF (ideal)”; wherein ratio of VREF/VREF (ideal) is represented the difference) between the digital estimate of output signal (digital Vout of ADC 202) and an ideal digital output signal (Paragraph 0057 discloses VREF (ideal)).
However, Lazarov et al. do not disclose: combining the error in the digital estimate of the output signal with the unadjusted voltage reference in order to generate the adjusted output signal.
Fig. 7 of Huang et al. discloses a method of generating of an adjusted output signal (output of adjust output signal of 313), the method comprising: (ADC 224) a digital estimate (digital output of ADC 224) based on an analog (analog input of ADC 224); deriving an error (Accumulating and average module 332 output error signal of absolute signal lVil) based on a difference (311) between the digital estimate of output signal (digital output of ADC 224) and an ideal digital output signal (desired signal bi); an unadjusted voltage reference (absolute lVol reference) and combining (510) of the error in the digital estimate of the output signal (Accumulating and average module 332 output error signal absolute lVil) with the unadjusted voltage reference (absolute lVol reference) in order to generate the adjusted output signal (adjusted output signal of 313).
Lazarov et al. and Huang et al. are common subject matter of calibration of digital signal from an ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Huang et al. into Lazarov et al. for the purpose of calibrating the offset errors and gain errors among the inner converters (paragraph 0006 of Huang et al.).
Regarding claim 2. Lazarov et al. and Huang et al. applied to claim 1 above, Fig. 2 of Lazarov et al. further disclose; receiving the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026) and at least one of the first calibrated voltage (VCAL_PNP) and the second calibrated voltage (VCAL_NPN).
Regarding claim 3. Lazarov et al. and Huang et al. applied to claim 2 above, Fig. 2 of Lazarov et al. further disclose: receiving the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026), the first calibrated voltage (VCAL_PNP) and the second calibrated voltage (VCAL_NPN).
Regarding claim 4. Lazarov et al. and Huang et al. applied to claim 1 above, Fig. 2 of Lazarov et al. further disclose wherein determining an estimate of the output signal comprises performing an iterative algorithm (paragraph 0081 “next iteration for a temperature estimate can be calculated after the gain correction factor G is determined from (25) and may include the equation T=α(T)Gc.sub.0.”).
Regarding claim 5. Lazarov et al. and Huang et al. applied to claim 4 above, Fig. 2 of Lazarov et al. further disclose wherein the iterative algorithm (paragraph 0081) produces a digital code (digital code of corrected ADC result) for adjusting the analog representation (selection of VCAL_PNP and VCAL_NPN. See Fig. 3A and 3P) of the output signal (Vout) to reach the ideal output signal (Paragraph 0057 discloses VREF (ideal)).
Regarding claim 6. Lazarov et al. and Huang et al. applied to claim 1 above, Fig. 3A and Fig. 3B of Lazarov et al. further disclose wherein determining an estimate of the output signal (corrected ADC result) comprises performing a single step algorithm (single step algorithm for VCAL_PNP in Fig. 3A and single step algorithm for VCAL_NPN in Fig. 3B).
Regarding claim 7. Lazarov et al. and Huang et al. applied to claim 1 above, Fig. 2 of Lazarov et al. further disclose wherein determining (determined by ADC) a digital estimate of the output signal (digital output of 212 for corrected ADC result) comprises determining a digital estimate (digital estimate of 212) of the at least one of the first calibrated voltage (VCAL_PNP), the second calibrated voltage (VCAL_NPN), and the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026).
8. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lazarov et al. and Huang et al. applied to claim 1 above, in further vier of Norouzpourshirazi Pub. No. 2024/0106448.
Lazarov et al. and Huang et al. applied to claim 1 above do not disclose comprising: low pass filtering the unadjusted voltage reference in order to remove noise aliasing from unadjusted voltage reference.
Fig. 1 of Norouzpourshirazi discloses an analog-to-digital converter (ADC 102) comprising low pass filtering (112, 114; paragraph 0022) an unadjusted voltage reference (VR) in order to remove noise aliasing (remove high frequency noise by low-pass filter 112 and 114) from unadjusted voltage reference (VR).
Lazarov et al., Huang et al. and Norouzpourshirazi are common subject matter of unadjusted voltage for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Norouzpourshirazi into Lazarov et al./Huang et al. for the purpose providing low-pass filter for unadjusted reference voltage to remove high frequency noise of unadjusted reference voltage as suggested by Fig. of Norouzpourshirazi.
10. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lazarov et al. and Huang et al. applied to claim 1 above, in further vier of Thompson U.S. patent No. 5,028,924.
Lazarov et al. and Huang et al. applied to claim 1 above do not discloses shaping a noise profile of the adjusted output signal using a first order integration, a second order or a higher order integration.
Fig. 1 of Thompson discloses an analog to digital converter (14; see Fig. 2) comprising shaping a noise profile (Col. 9 lines 7-8b discloses “compensates for the in-band noise in the 16-bit digital output”) of and adjusted output signal (compensated output signal of 36) using a first order integration (16), a second order (20) or a higher order integration (24).
Lazarov et al., Huang et al. and Thompson are common subject matter of compensated digital signal for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Thompson into Lazarov et al./Huang et al. for the purpose providing an improved A/D converter wherein a digital correction signal is applied to at least one digital integrator to compensate for the gain mismatches in ADC stage thereby reducing the in-band quantization error and increasing the resolution of the multi-bit digital output signal (Col. 3 lines 5-12 of Thompson).
11. Claims 10-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lazarov et al. Pub. No. 2019/0041471 in view of Bogner U.S. patent No. 8,766,833.
Regarding claim 10. Fig. 4 of Lazarov et al. discloses a circuit (400) for generating an adjusted output signal (Vout 214) , the circuit comprising: a calibration circuit (208) providing at least one of a first calibrated pnp voltage (VCAL_PNP) based on a base-emitter voltage of one or more pnp transistors (PNP transistor) , a second calibrated npn voltage (VCAL_NPN) based on a base-emitter voltage of one or more npn transistors (NPN transistor) , and a voltage (VPAT) that is proportional to absolute temperature (paragraph 0026); an analog-to-digital converter, ADC , system (ADC 202) coupled to the calibration circuit (208), and configured to: determine a digital estimate (Digital Vout of ADC 202) of the output signal (Vout) based on an analog (analog Vin) representation of the output signal (Vout) , and based on the at least one of the first calibrated voltage (VCAL_PNP), the second calibrated voltage (VCAL_NPN) , and the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026); and derive an error (paragraph 0025 discloses “gain correction factor G is calculated to bring the error in the measurement of sense voltage Vsns_n to zero”) in the digital estimate (digital Vout of ADC 202) of the output signal (Vout 214) based on a difference ((paragraph 0057 discloses “digital gain correction is determines to scaled the non-ideal ADC output codeADC: G=VREF/VREF (ideal)”; wherein ratio of VREF/VREF (ideal) is represented the difference)) between the digital estimate (digital Vout of ADC 202) of output signal (Vout 214) and an ideal digital output signal (Paragraph 0057 discloses “VREF (ideal)”); a digital-to-analog converter, DAC (DAC 266) , configured to output an analog (analog output of DAC 216) representation of the error (error (paragraph 0025 discloses “gain correction factor G is calculated to bring the error in the measurement of sense voltage Vsns_n to zero”); and an unadjusted voltage reference generator (ADC Vref 204) configured to generate an unadjusted voltage reference (Vref of 204) in order to generate the adjusted output signal (Vout 214).
However, Lazarov et al. do not disclose the unadjusted voltage reference (Vref of 204) that is combined together with the output of the DAC in order to generate the adjusted output signal.
Fig. 1b of Bogner discloses an ADC converter (Col. 2 lines 65-66) comprising: the unadjusted voltage reference (Vref of 154) that is combined together with an output of a DAC (Cdac) in order to generate an adjusted output signal (adjusted output signal at combination input node of comparator 134).
Lazarov et al. and Bogner are common subject matter of calibration of digital signal for an ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Bogner into Lazarov et al. for the purpose of summing an output of the DAC with the first reference voltage to produce a summed output, comparing the summed output to a threshold, and adjusting the programmable reference voltage until the summed output is within a predetermined range of the threshold (Col. 1 lines 51-56 of Bogner et al.).
Regarding claim 11. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses: wherein the calibration circuit (208) provides the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026) and at least one of the first calibrated voltage (VCAL_PNP) and the second calibrated voltage (VCAL_NPN).
Regarding claim 12. Lazarov et al. and Bogner applied to claim 11 above, Fig. 4 of Lazarov et al. further discloses: wherein the calibration circuit (208) provides the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026), the first calibrated voltage (VCAL_PNP) and the second calibrated voltage (VCAL_NPN).
Regarding claim 13. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses: wherein the ADC system (400) comprises: a multiplexer (MUX 206) configured to provide an analog signal (analog Vin) selected from the first calibrated pnp voltage (VCAL_PNP), and the second calibrated npn voltage (VCAL_NPN) ; and an ADC (ADC 202) configured to generate a digital estimate (Digital Vout of ADC 202) of the analog signal (analog Vin) selected by the multiplexer (MUX 206) and a digital estimate (digital Vout of ADC 202) of an analog (analog Vin) representation of the output signal (Vout 214).
Regarding claim 14. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses: wherein the ADC system (400) comprises a processor (202) configured to determine a digital estimate (digital Vout) of the output signal (Vout 214) based on the digital estimate (digital Vout) of the analog signal (Vin) selected by a multiplexer (206) and the digital estimate (digital Vout) of the analog (Vin) representation of the output signal (Vout 214).
Regarding claim 15. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses wherein the ADC system (400) is configured to determine a digital estimate (digital output of 212) of the output signal (Vout 214) by performing an iterative algorithm (paragraph 0081 “next iteration for a temperature estimate can be calculated after the gain correction factor G is determined from (25) and may include the equation T=α(T)Gc.sub.0.”).
Regarding claim 16. Lazarov et al. and Bogner applied to claim 15 above, Fig. 4 of Lazarov et al. further discloses wherein the iterative algorithm (paragraph 0081 “next iteration for a temperature estimate can be calculated after the gain correction factor G is determined from (25) and may include the equation T=α(T)Gc.sub.0.”) produces a digital code (digital code from 210 to MUX 206) for adjusting (change the selection of MUX) the analog representation output signal (Vin) to reach the ideal output signal (Paragraph 0057 discloses “VREF (ideal)”).
Regarding claim 17. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses wherein the ADC system (400) is configured to determine an estimate of the output signal (Vout 214) by performing a single step algorithm (single step algorithm for VCAL_PNP in Fig. 3A and single step algorithm for VCAL_NPN in Fig. 3B).
Regarding claim 18. Lazarov et al. and Bogner applied to claim 10 above, Fig. 4 of Lazarov et al. further discloses wherein the ADC system (400) is configured to determine a digital estimate (digital output of 212) of the output signal (Vout 214) comprises determining a digital estimate (digital output of 212) of the at least one of the first calibrated voltage (VCAL_PNP), the second calibrated voltage (VCAL_NPN), and the voltage (VPTAT) that is proportional to absolute temperature (paragraph 0026).
Regarding claim 20. Lazarov et al. and Bogner applied to claim 10 above, Fig. 1b of Bogner further discloses comprising a digital integrator configured to shape a noise profile of the adjusted output signal (no subject matter considered in this claim, because alternative subject matter followed and/or in the claim) and/or an adder (summing node on input comparator 134) configured to sum the output of the DAC (output of Cdca) and the unadjusted voltage reference (Vref).
Contact Information
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/28/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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