Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on Chinese application number CN202410209432.7 filed in China on February 26th, 2024. It is noted, however, that an attempt to retrieve the foreign priority document by the US Patent and Trademark Office electronically on July 26th, 2025 was not successful, and that applicant has not filed a certified copy of the foreign priority document as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 11-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over TAKANO, (US 20200026466) in view of Balakrishnan et al. (US 2024/0111422).
Regarding independent claim 1, TAKANO discloses an operation method of a memory system (FIGs. 3 and 7-9, operation processes of operating memory system 1, FIG. 1, with NAND memory 200 and memory controller 100 using [0036] firmware program stored memory system 1), comprising:
setting, to a readable state, part of N channel queues corresponding to a same channel (FIGs. 1 and 3, each channel 0-3 has 4 banks #0-#3, each channel has its own NAND controller 140-0 to 140-3, each NAND controller 140 in FIG. 5 has 4 Queue Blocks 150 corresponding to 4 banks. FIG. 3, each bank can be locked for read commands, [0054], “The memory controller 100 can lock the bank arbitration. Locking the bank arbitration represents setting one bank as an access target and disabling the switch of the access target to a subsequent bank.” Thus, there are 4 channel queues for each channel, and each channel queue can be set or locked to a readable state, while other channel queues are disabled from reading),
wherein the N channel queues comprise read commands received by a controller, addresses comprised in the read commands in different channel queues correspond to different of the memory dies (FIGs. 4-5, [0064], each of 4 queue blocks 150 receives commands from command generator 111 from CPU 110. [0077], command may be asynchronous read commands with address information. [0024], “The memory controller 100 can individually control the channels.” [0027], “it is assumed that one bank includes one memory chip 210” [0059], “The command generator 111 generates a command for the memory chip 210 in response to an access request received form the host 2. The command generator 111 can generate a read command…. The read command includes an asynchronous read command. The command generator 111 transmits the generated command to a NAND controller 140 corresponding to the channel to which a target memory chip 210 is connected.” Thus, address information in the read commands as generated corresponds to specific “target memory chip” or die),
the readable state indicates that the read commands in a corresponding channel queue are allowed to be read ([0054], “The memory controller 100 can lock the bank arbitration. Locking the bank arbitration represents setting one bank as an access target and disabling the switch of the access target to a subsequent bank.” [0064]-[0065], “Each of the queue blocks 150 receives a command, distributed from the command generator 111, for its corresponding bank, and retains the command in an inside queue (a main queue 151 or a plurality of sub-queues 154) until transmitting the command. The NAND controller 140-0 further includes a bank arbiter 160. The bank arbiter 160 selects one of the four queue blocks 150 in accordance with a selection signal from the arbitrator 112. The bank arbiter 160 enables the transmission of a command from the selected queue block 150. By such an operation, one of the four banks (the bank #0 to the bank #3) is set or selected as an access target. The bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 in accordance with the selection signal from the arbitrator 112.” Thus, the queue block corresponding to the target bank under access lock is allowed to be read for its read commands and commands are transmitted to the target bank. each channel queue can be set or locked to a readable state to allow 1 bank to be read/accessed, while other channel queues and other banks are disabled from reading/transmitting commands), and
N is an integer greater than or equal to 2 (FIGs. 1 and 3, each channel 0-3 has 4 banks #0-#3, each channel has its own NAND controller 140-0 to 140-3, each NAND controller 140 in FIG. 5 has 4 Queue Blocks 150 corresponding to 4 banks. Thus, there are 4 channel queues for each channel, N=4 here);
acquiring a read command in a channel queue in the readable state among the N channel queues; and performing a read operation in a corresponding memory in the memory system according to the acquired read command ([0145], “multiple asynchronous read commands are continuously enqueued in the main queue 151…. the asynchronous read commands are transmitted to the memory chip 210 …, and are executed.”).
Takano teaches that each channel queue of the N channel queues corresponds to a memory chip 210, see figure 1, and paragraph 0063, and that each memory chip 210 includes a plurality of sub- arrays which may be referred to as planes, see paragraphs 0039 and 0040. However, Takano does not expressly teach that each channel queue of the N channel queues corresponds to multiple memory dies.
With respect to claim 1, Balakrishnan teaches that each of a plurality of banks can comprise a plurality of planes, and each of the plurality of planes can comprise a plurality of dies.
As of the earliest effective filing date of the invention, it would have been obvious to implement the planes of Takano as a plurality of dies.
The rationale for doing so would have been a known technique for implementing planes in a NAND memory system.
Therefore, it would have been obvious to combine Balakrishnan with Takano to obtain the invention as recited in claims 1-5, 9, 11-15, and 19-20.
Regarding claim 2, TAKANO discloses the method of claim 1, wherein the addresses comprised in the read commands correspond to dies connected to one or more CE pins in the same channel ([0023], “Each of the channels includes a wiring group including I/O signal lines and control signal lines. The I/O signal lines are, for example, signal lines through which data, addresses, and commands are transmitted and received. The control signal lines are, for example, … a chip enable (CE) signal or a chip select (CS) signal are transmitted and received.” [0024], “The memory controller 100 can individually control the channels.” [0027], “it is assumed that one bank includes one memory chip 210” [0059], “The command generator 111 generates a command for the memory chip 210 in response to an access request received form the host 2. The command generator 111 can generate a read command…. The read command includes an asynchronous read command. The command generator 111 transmits the generated command to a NAND controller 140 corresponding to the channel to which a target memory chip 210 is connected.” Thus, address information in the read commands as generated corresponds to specific “target memory chip” or die, connected to one or more CE pins) .
Regarding claim 3, TAKANO discloses the method of claim 2, wherein the N channel queues comprise a first channel queue and a second channel queue (FIGs. 1 and 3, each channel 0-3 has 4 banks #0-#3, each channel has its own NAND controller 140-0 to 140-3, each NAND controller 140 in FIG. 5 has 4 Queue Blocks 150 corresponding to 4 banks. Thus, there are 4 channel queues for each channel, N=4 here);
addresses comprised in read commands in the first channel queue correspond to a die connected to a CE pin, whose number belongs to a first number set, in the same channel; and addresses comprised in read commands in the second channel queue correspond to a die connected to a CE pin, whose number belongs to a second number set, in the same channel (FIGs. 1 and 3, each channel 0-3 has 4 banks #0-#3, each channel has its own NAND controller 140-0 to 140-3, each NAND controller 140 in FIG. 5 has 4 Queue Blocks 150 corresponding to 4 banks. [0023], “Each of the channels includes a wiring group including I/O signal lines and control signal lines. The I/O signal lines are, for example, signal lines through which data, addresses, and commands are transmitted and received. The control signal lines are, for example, … a chip enable (CE) signal or a chip select (CS) signal are transmitted and received.” [0024], “The memory controller 100 can individually control the channels.” [0027], “it is assumed that one bank includes one memory chip 210” [0059], “The command generator 111 generates a command for the memory chip 210 in response to an access request received form the host 2. The command generator 111 can generate a read command…. The read command includes an asynchronous read command. The command generator 111 transmits the generated command to a NAND controller 140 corresponding to the channel to which a target memory chip 210 is connected.” Thus, address information in the read commands as generated corresponds to specific “target memory chip” or die, connected to one or more CE pins. Thus, address for each channel queue correspond to a die with its own CE/CS pins, its own CE/CS pin number belongs to its own number set).
Regarding claim 4, TAKANO discloses the method of claim 1, wherein setting, to the readable state, the part of the N channel queues corresponding to the same channel comprises: setting, to the readable state, the N channel queues corresponding to the same channel in turn according to time periods ([0052] As illustrated in FIG. 3, the memory controller 100 sets or selects the bank #0, the bank #1, the bank #2, and the bank #3 as access targets in this order. The memory controller 100 sets or selects the bank #0 as an access target after the bank #3. After transmitting a command to the bank to access and during the execution of the operation of the bank in response to the command, the memory controller 100 can switch the bank to access to a next bank. [0054] The memory controller 100 can lock the bank arbitration. Locking the bank arbitration represents setting one bank as an access target and disabling the switch of the access target to a subsequent bank. After releasing the lock, the memory controller 100 can switch the access target to a subsequent bank. In addition, the locking of the bank arbitration may include, for example, a low-level lock function and a high-level lock function. The bank locked by the low-level lock function can be automatically released from being locked if the bank is not ready for a subsequent operation command. Thus, the banks are individually locked /set to readable state in turn, one after another. Time periods is implicit since timing of command issuing and execution is controlled by the memory controller, which has to wait for 1 set of commands for 1 bank to finish before changing to next bank).
Regarding claim 5, TAKANO discloses the method of claim 4, wherein setting, to the readable state, the N channel queues corresponding to the same channel in turn according to the time periods comprises: within one of the time periods, setting a third channel queue of the N channel queues to a readable state, and setting other channel queues of the N channel queues other than the third channel queue to a non-readable state, wherein the non-readable state indicates that the read commands in corresponding channel queues are not allowed to be read, and wherein within two adjacent time periods, the corresponding channel queues set to the readable state are different (FIGs. 1 and 3, each channel 0-3 has 4 banks #0-#3, each channel has its own NAND controller 140-0 to 140-3, each NAND controller 140 in FIG. 5 has 4 Queue Blocks 150 corresponding to 4 banks. FIG. 3, each bank can be locked for read commands, [0054], “The memory controller 100 can lock the bank arbitration. Locking the bank arbitration represents setting one bank as an access target and disabling the switch of the access target to a subsequent bank.” Thus, there are 4 channel queues for each channel, and each channel queue can be set or locked to a readable state, while other channel queues are disabled from reading. the banks are individually locked /set to readable state in turn, one after another. Time periods is implicit since timing of command issuing and execution is controlled by the memory controller, which has to wait for 1 set of commands for 1 bank to finish before changing to next bank).
Regarding claim 9, TAKANO discloses the method of claim 1, further comprising before setting, to the readable state, the part of the N channel queues corresponding to the same channel: receiving a first instruction, wherein the first instruction indicates enabling of a function to set the part of the N channel queues to the readable state (“instruction indicates enabling of a function” here is interpreted as any instruction for the bank selection operation. [0036] The CPU 110 is a processor that operates by a program (firmware program) stored in the memory system 1 in advance. The CPU 110 implements various functions including command generation in accordance with the firmware program. [0059] The command generator 111 generates a command for the memory chip 210 in response to an access request received form the host 2. The command generator 111 can generate a write command, a read command, and an erase command. The read command includes an asynchronous read command. The command generator 111 transmits the generated command to a NAND controller 140 corresponding to the channel to which a target memory chip 210 is connected. That is, the command generator 111 can generate various commands to distribute commands to the four NAND controllers 140. Thus, instructions for command generation enables bank selection/distribution).
Regarding independent claim 11, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding claim 12, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Regarding claim 13, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
Regarding claim 14, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
Regarding claim 15, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
Regarding claim 19, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
Regarding independent claim 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over TAKANO in view of Balakrishnan et al. (US 2024/0111422) and further in view of Cowles et al., US Patent Number 5263003 (herein “COWLES”).
Regarding claim 6, TAKANO discloses the method of claim 5, wherein the readable states correspond to the N channel queues one to one, within one of the time periods, setting the third channel queue of the N channel queues to the readable state, and setting the other channel queues of the N channel queues other than the third channel queue to the non-readable state (FIG. 3, [0054], “The memory controller 100 can lock the bank arbitration. Locking the bank arbitration represents setting one bank as an access target and disabling the switch of the access target to a subsequent bank.” Implicitly, the lock state or disable state of each bank must be stored in the controller, and each of the 4 lock /disable state for 4 banks/channels queues in FIG. 3 is a bit corresponding to each bank. Thus 1 bank/ 3rd channel queue is locked as “setting one bank”, while other banks /channel queues are disabled. Time periods is implicit since timing of command issuing and execution is controlled by the memory controller, which has to wait for 1 set of commands for 1 bank to finish before changing to next bank).
TAKANO does not explicitly disclose wherein the controller comprises a readable state register, and N bits in the readable state register; and setting, to a first numerical value, a bit in the readable state register that corresponds to the third channel queue; and setting, to a second numerical value, bits in the readable state register that correspond to the other channel queues other than the third channel queue.
COWLES discloses wherein the controller comprises a readable state register, and N bits in the readable state register; and setting, to a first numerical value, a bit in the readable state register that corresponds to the third channel queue; and setting, to a second numerical value, bits in the readable state register that correspond to the other channel queues other than the third channel queue (FIG. 3, Control register 89, col. 9 lines 28-46, “The lines of the processor section data bus 63 are connected to the input of the control register 89 which, upon being enabled by a signal on the control bus 62, stores the data carried by those lines. As will be described, one data bit stored in the control register 89 determines whether the flash memory 55 operates in the interleaved bank access mode or in a single bank access mode and in latter mode which bank is to be accessed. …. In the single bank access mode one and only one of the memory banks 71 or 72 is being accessed. In either accessing mode, the second microprocessor 54 can operate in the burst or sequential addressing modes. Other control register bits individually select the memory banks 71 and 72 for erasure and programming. The outputs of the control register 89 are coupled to the bank multiplexer 84 and the flash memory control 88.” Thus, individual banks/queues are selected by the individual bits in the control register corresponding to the N channel queues/banks one to one, and the register bits are set to different numerical value depending on which bit is selected).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify TAKANO and Balakrishnan’s multi-channel multi-bank memory system to further include COWLES’ bank interleaving control register bits, to increase system performance (see COWLES col. 3 lines 35-39).
Regarding claim 7, TAKANO discloses the method of claim 6, wherein the readable state register is disposed in a flash control unit of the controller; or the readable state register is disposed outside the flash control unit of the controller (this is inherent, because the bank select control register must be either inside or outside of the flash control unit of the controller).
Regarding claim 8, TAKANO discloses the method of claim 6, wherein acquiring the read command in the channel queue in the readable state among the N channel queues comprises: reading numerical values of the N bits in the readable state register ([0053] Arbitrating or setting the access target in a unit of a bank is referred to as a bank arbitration. [0054] The memory controller 100 can lock the bank arbitration. [0061] The arbitrator 112 executes the bank arbitration and the sub-bank arbitration.); and
reading the read command from the channel queue corresponding to the bit, whose numerical value is the first numerical value, among the N bits ([0064]-[0065], “Each of the queue blocks 150 receives a command, distributed from the command generator 111, for its corresponding bank, and retains the command in an inside queue (a main queue 151 or a plurality of sub-queues 154) until transmitting the command. The NAND controller 140-0 further includes a bank arbiter 160. The bank arbiter 160 selects one of the four queue blocks 150 in accordance with a selection signal from the arbitrator 112. The bank arbiter 160 enables the transmission of a command from the selected queue block 150. By such an operation, one of the four banks (the bank #0 to the bank #3) is set or selected as an access target. The bank arbiter 160 implements the bank arbitration by sequentially selecting the four queue blocks 150 in accordance with the selection signal from the arbitrator 112.” Thus, the queue block corresponding to the target bank under access lock is read for its read commands and commands are transmitted to the target bank).
Regarding claim 16, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
Regarding claim 17, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
Regarding claim 18, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over TAKANO in view of Balakrishnan et al. (US 2024/0111422) and further in view of Flynn et al., US Patent Application Number 20080229079 (herein “FLYNN”).
Regarding claim 10, TAKANO discloses the method of claim 4, but does not explicitly disclose further comprising, wherein before setting, to the readable state, the N channel queues corresponding to the same channel in turn according to the time periods, the method further comprises: receiving a second instruction, wherein the second instruction indicates a time duration of the time periods; and setting, to the readable state, the N channel queues corresponding to the same channel in turn according to the time periods comprises: according to the time duration of the time periods, setting the N channel queues to the readable state in turn according to the time periods.
FLYNN discloses wherein before setting, to the readable state, the N channel queues corresponding to the same channel in turn according to the time periods, the method further comprises: receiving a second instruction, wherein the second instruction indicates a time duration of the time periods; and setting, to the readable state, the N channel queues corresponding to the same channel in turn according to the time periods comprises: according to the time duration of the time periods, setting the N channel queues to the readable state in turn according to the time periods ([0175], “The bus arbiter 420 coordinates the various command types and data access modes so that only an appropriate command type or corresponding data is on the bus at any given time.… Beneficially, the bus arbiter 420 uses timing information, such as predicted command execution times, along with status information received concerning bank 214 status to coordinate execution of the various commands on the bus with the goal of minimizing or eliminating idle time of the busses.” E.g. bus arbiter 420 uses predicted command execution time to coordinate /schedule commands in the queues, thus receiving instruction indicating time duration, and according to the time durations, setting the command queue states).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify TAKANO and Balakrishnan’s multi-channel multi-bank memory system to further include FLYNN’s bank interleaving implementation, to allow efficient managing of commands for solid-state storage (see FLYNN [0010]).
Response to Arguments
Applicant’s arguments, see page of the remarks filed 11/21/2025, with respect to the objection to the title, the objections to the claims, the rejections under 112(b), and the rejection under 101 have been fully considered and are persuasive. Said rejections and objections have been withdrawn.
Applicant’s arguments, see page 10 of the remarks filed 11/21/2025, with respect to the rejection(s) of claim(s) 1-5, 9, 11-15, and 19-20 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Balakrishnan et al. (US 2024/0111422).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135