DETAILED ACTION
This communication is in response to the application filed on January 8, 2026 in which claims 1-20 are pending in the application. Claims 1, 8, and 15 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application claims the benefit of U.S. Provisional Patent Application No. 63/539,758, filed September 21, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 8, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This Office Action is in response to the applicant’s remarks and arguments filed on January 8, 2026.
a. Claims 1, 8 and 15 were amended. No claims were canceled or added. Claims 1-20 remain pending in the application. Claims 1-20 are being considered on the merits.
b. The rejection of claims 1-2, 4-9 and 18-20 under 35 USC 102 has been withdrawn due to the amendment to the claims filed on January 8, 2026.
Response to Arguments
The applicant’s remarks and/or arguments, filed on Janaury 8, 2026 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant's arguments in the applicant’s remarks and amendments of independent claims 1, 8 and 15, found on pages 7-9 and filed on January 8, 2026, have been fully considered and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 102 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art: (US 20220189544 A1 A1) issued to Nguyen et al., and in view of the previously cited prior art(s). References Ahirwar and Nguyen, alone or in combination, discloses each element of the claims highlighted by applicant.
For further details, please see below claims rejections under 35 USC 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-9, 11-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahirwar et al (US 2020/0264810 A1) and Nguyen et al. (US 20220189544 A1).
As per claim 1, Ahirwar discloses a method comprising:
receiving, from a host system, host data to be programmed to a plurality of memory cells associated with a wordline of a memory device [Para 0020, “Write controller 106 receives write requests from the processor. The write controller 106 first divides the data into sections or words of Q*M+P bit length. Words of this length are stored together over Q cells…”];
dividing a sequence of bits of the host data into a plurality of partitions, wherein each partition comprises a portion of the sequence of bits [Para 0020, “The write controller 106 first divides the data into sections or words of Q*M+P bit length. Words of this length are stored together over Q cells…”];
dividing the portion of the sequence of bits associated with each of the plurality of partitions into a respective plurality of sub-partitions, wherein each sub-partition comprises a subset of the portion associated with a given partition [Para 0025, “The data (or word) of Q*M+P bit length is divided further into Q portions of M bit length (to be stored directly in Q cells) and distributed bits P.” It is to be noted that Each partition/word is divided into portions/sub-partitions (Q portions of M bits, and distributed bits P).];
querying, using the subset of the portion associated with each sub-partition of the plurality of sub-partitions, a modulation mappings data structure to obtain one or more modulation mappings to be applied to the subset of the portion associated with a respective sub-partition of the plurality of sub-partitions, [Para 0025, “The write controller then identifies the first Q empty cells… The controller selects a value of n for each cell q from a lookup table or any other appropriate method that correlates values of L_q and M to n.”; Para 0049, “Mapping of the value of the P bits to the set partition vector can be performed via a look up table or other direct mapping.” It is to be noted that Modulation mapping is performed via lookup table, mapping distributed bits to partition vectors and cell levels. Lookup tables (modulation mappings data structure) are used to obtain the mappings for each sub-partition.];
modifying, based on the one or more modulation mappings, the subset of the portion associated with host data of each sub-partition of the plurality of sub-partitions [Para 0051, “For each of Q cells the partitioned subset identifier L_q … and the value of the M bits … are mapped to a level n … Mapping may be via a lookup table or a logic operation may be performed.” It is to be noted that Data for each sub-partition is modified by mapping to a specific level (modulation mapping).];
and writing the modified subset of the portion associated with host data of each sub-partition to the plurality of memory cells associated with the wordline [Para 0053, “For each of Q cells a threshold voltage V_th is selected based on level n … each of the Q threshold voltages V_th are written by outputting corresponding write signals in the write channel to the correct page, block, word line, and bit line.” It is to be noted that Modified data is written to the memory cells associated with the wordline.].
Ahirwar discloses does not specifically teach wherein each modulation mapping flips one or more bits of the subset of the portion associated with the respective sub-partition, and wherein two or more modulation mappings are combined [Para [0015], “Set partitioning and assigning bit values to the partitioned subsets determined via code modulation inherently protects the stored bits from bit flip errors by effectively increasing the distance between threshold voltages…”; Para [0032], “By selecting levels as divergent as possible for each of the bits using a method like TCM (or another appropriate partitioning method), required ECC is reduced.”]. The combination of multiple mappings is implicit in the use of partition vectors and code modulation
The reference describes code modulation and set partitioning which may flip bits, but does not always explicitly state “flipping” as the mapping method as recited in the claim.
Nguyen discloses wherein each modulation mapping flips one or more bits of the subset of the portion associated with the respective sub-partition as recited in the claim [Para [0046], “the programming manager 113 generates the Nth data group by applying XOR (or XNOR) on the N-1 data groups.”; Para [0058], “data bits 161, 163, . . . , 165 form an exclusive or relation, where any of the data bit (e.g., 161 or 163) is equal to the result of applying XOR operation 201 to the other data bits.”]
Both Ahirwar and Nguyen are in the same field of endeavor as they are both in the set partitioning and assigning bits to the partitions in data memory control art and, therefore, are combinable/modifiable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Ahirwar with the teachings of Nguyen in order to include “state flipping” as the modulation mapping method.
Modification would optimize operation of the system by reducing the number of programming operations of the data having a predetermined or determined value on the memory device, thereby maintaining adequate level of performance of the memory system.
As per claim 2, Ahirwar discloses the method of claim 1, wherein each entry of a sub-partition mapping data structure comprises the one or more modulation mappings [Para 0049, “Mapping of the value of the P bits to the set partition vector can be performed via a look up table or other direct mapping.” It is to be noted that the lookup table acts as a data structure mapping distributed bits (P) to partition vectors (modulation mappings).].
As per claim 4, Ahirwar discloses the method of claim 1, wherein the host data is divided into the plurality of partitions based on a first predetermined value [Para 0020, “The write controller 106 first divides the data into sections or words of Q*M+P bit length.”].
As per claim 5, Ahirwar discloses the method of claim 1, wherein each partition of the plurality of partitions is divided into the plurality of sub-partitions based on a second predetermined value [Para 0025, “The data (or word) of Q*M+P bit length is divided further into Q portions of M bit length (to be stored directly in Q cells) and distributed bits P.”].
As per claim 6, Ahirwar discloses the method of claim 1, wherein writing the modified host data of each sub-partition to the plurality of memory cells associated with the wordline comprises appending, to the modified host data, a mapping value representing an entry of the sub-partition mapping data structure associated with the one or more modulation mappings used to modify the host data [Para 0049, “Mapping of the value of the P bits to the set partition vector can be performed via a look up table or other direct mapping.”; Para 0022, “The Q cells can be physically separated when required by available space, such as written both at the end of a page A and at the beginning of a page B. However, physical compactness increases the speed at which distributed bits can be both written and read. The write controller 106 writes bits to empty blocks on new pages as dictated by the cell management logic 114, accomplishing compactness during the initial write. However, when the Q cells are scheduled to be re-written on a new page by the cell management logic 114, the data addressing logic 110 ensures that the grouped cells are re-written together based on an identifier, tag, or lookup table maintained by the Q partitioned cells identifier logic 112.”].
As per claim 7, Ahirwar discloses the method of claim 6, wherein responsive to receiving a request to read host data from the plurality of memory cells associated with the wordline, obtaining the one or more modulation mappings from an entry of the sub-partition mapping data structure identified by the appended mapping value of the modified subset of the portion host data; and reverting, using the one or more modulation mappings, the modified subset of the portion host data back to the subset of the portion host data [Para 0026, “The read controller 104 queries the data addressing logic 110 to find the current storage location of the Q cells grouped by the Q partitioned cells identifier logic 112. Once the cells are identified, each of q cells (where 1<q<Q) is read and V_th determined. The controller then calculates n or correlates the measured V_th to n. Once the value of n for each cell q is known, the read controller 104 determines partitioned subset identifier Lq for each cell. The read controller 104 then calculates the set partition vector {L_1, L_2, …} and looks up or calculates the value of the P partitioned bits based on the value of the set partition vector. … The read controller 104 then assembles all M bits of Q cells and P partitioned bits and reports these bits to the requesting processor.”]
As per claim 8, the claim is rejected using the same rationale as noted above for claim 1. Ahirwar further discloses a system comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices [Para 0018, “An SSD controller 102 is depicted with selected components and logical operations for level partitioning and fractional bit storage. … The components of SSD controller 102 can be contained on the SSD itself, on a processor in communication with the SSD, or distributed between locations.”].
As per claim 9, the claim is rejected using the same rationale as noted above for claim 2.
As per claim 11, the claim is rejected using the same rationale as noted above for claim 4.
As per claim 12, the claim is rejected using the same rationale as noted above for claim 5.
As per claim 13, the claim is rejected using the same rationale as noted above for claim 6.
As per claim 14, the claim is rejected using the same rationale as noted above for claim 7.
As per claim 15, the claim is rejected using the same rationale as noted above for claim 1.
As per claim 16, the claim is rejected using the same rationale as noted above for claim 2.
As per claim 18, the claim is rejected using the same rationale as noted above for claims 4 and 5.
As per claim 19, the claim is rejected using the same rationale as noted above for claim 6.
As per claim 20, the claim is rejected using the same rationale as noted above for claim 7.
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahirwar et al (US 2020/0264810 A1 and Nguyen et al. (US 20220189544 A1) and Choi et al (US 2021/0034251 A1.
As per claims 3, 10 and 17, Ahirwar and Nguyen disclose the claimed invention as detailed above for claim 1. Ahirwar further discloses the method of claim 1, wherein each modulation mapping flips one or more bits of the host data within a sub-partition of the plurality of sub-partitions [Para 0015, “Set partitioning and assigning bit values to the partitioned subsets determined via code modulation inherently protects the stored bits from bit flip errors…”; Para 0032, “By selecting levels as divergent as possible for each of the bits using a method like TCM (or another appropriate partitioning method), required ECC is reduced.”].
Ahirwar teaches the method of claims 1 and 3 as detailed above. However, Ahirwar describes assigning bit values and code modulation, which can involve bit flipping, but does not explicitly state “flipping bits” as the modulation mapping method as required by the claims.
Choi discloses “flipping bits” as the modulation mapping method [Para 0031, A state shaping operation may be defined as an operation of... transforming the data DATA having the predetermined or determined value... so that the data DATA may have a different value; Para 0051; 0093]
Ahirwar, Nguyen and Choi are in the same field of endeavor and they are both in the set partitioning and assigning bits to the partitions in the data memory control and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Ahirwar and Nguyen with the teachings of Choi in order to include “flipping bits” as the modulation mapping method.
Modification would optimize operation of the system by reducing the number of programming operations of the data having a predetermined or determined value on the memory device, thereby maintaining adequate level of performance of the memory system as taught by Choi [Para 0031].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US 20220214804 A1) discloses The memory device includes: a memory cell region; and a data bus inversion (DBI) circuit configured to receive, from the memory cell region, data including multiple bits, select a group of bits from among the multiple bits in response to the partial read information, invert the group of bits to generate data including the inverted bits and transmit the data to the controller (Para 0010).
Zhao (DE 112019007656T5) discloses Signals communicated over channels 115 may be modulated using a number of different modulation schemes. A binary symbol (or binary level) or a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between external memory controller 105 and memory device 110 .
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
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July 21, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2162
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