DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 23 July 2024.
Claims 1-20 are pending and have been presented for examination.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: the limitation “… to local memory to be cache coherent with main memory of the host processor…” appears to contain a typo. The Examiner recommends amending the limitation to read “… [[to]]the local memory to be cache coherent with main memory of the host processor…” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6-12 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BAE (U.S. Patent Application Publication #2020/0142621) in view of BOLKHIVITIN (U.S. Patent Application Publication #2019/0171485).
1. BAE discloses A mass storage device coupled to a host processor (see [0033]: host device includes a central processing unit; [0039]: storage device; [0038]interface to provide a physical connection between the host device and the storage device), comprising: a non volatile storage media (see [0039]: storage device includes an SSD and stores data regardless of whether power is supplied – this is considered non-volatile media); a local memory coupled to the non volatile storage media (see [0049]: buffer), to local memory to be cache coherent with main memory of the host processor (see [0063]: the buffer is mapped to host virtual address space, access to the buffer is through the base address register, therefore all access to the buffer will retrieve a coherent version of the data, the data is physically stored in one memory and the buffer is mapped to host virtual address space); and a mass storage device processor (see [0041]: in-storage compute block to process data; [0048]: in-storage compute block can be a processor) to execute code as an additional processing core of the host processor (see BOLKHIVITIN below), wherein the mass storage device processor is to execute instructions out of the local memory (see [0072]: working memory to store data for driving the SSD controller, firmware loaded into the working memory to be executed by the processor), wherein the mass storage device processor is allocated main memory address space for contents of the local memory (see [0046]: buffer of the SSD is mapped to host virtual address space), and wherein operation of the mass storage device processor is compatible with the host processor from a code execution perspective (see BOLKHIVITIN below).
BOLKHIVITIN discloses the following limitations that are not taught by BAE: a mass storage device processor to execute code as an additional processing core of the host processor (see [0041]: host offloads processing tasks to the storage device; [0042]: source code from the host is sent to the storage device processor) wherein operation of the mass storage device processor is compatible with the host processor from a code execution perspective (see [0046]: the processing procedure is sent from the host to the storage device in source code form; [0052]: compiler is unnecessary when the source code is sent directly to the storage device). The host can send the processing procedure in byte code format or source code format. The configuration of the storage device will determine which format will provide the best performance. Using a source code format is a matter of design choice. When source code format is used, the execution of the host processor and storage processor are considered compatible from a code execution perspective since the storage processor can execute the source code sent from the host processor. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify BAE to have the storage processor execute code, as disclosed by BOLKHIVITIN. One of ordinary skill in the art would have been motivated to make such a modification to offload processing from the host and configure the processing procedure that provides the best performance, as taught by BOLKHIVITIN. BAE and BOLKHIVITIN are analogous/in the same field of endeavor as both references are as both references are directed to processing data within a storage device.
2. The mass storage device of claim 1, wherein the mass storage device processor has a same instruction set architecture as the host processor (see BOLKHIVITIN [0052]: when source code is sent for execution, it is clear the storage processor uses the same instruction set architecture since the storage processor can execute the same source code that can be executed by the host processor).
6. The mass storage device of claim 1, wherein the non volatile storage media includes any of: a flash memory; solid state storage; a hard disk drive; or a non volatile random access memory (see BAE [0039]: SSD).
7. The mass storage device of claim 1, wherein the non volatile storage media is to store a data set for execution by the mass storage device processor, based on program code stored in the non volatile storage media (see BAE [0085]: data is retrieved from the non-volatile memory and stored in the buffer, the in-storage computing block processes the data stored in the buffer).
8. The mass storage device of claim 7, wherein a thread of the host processor is to invoke the program code for execution by the mass storage device processor (see BOLKHIVITIN [0041]: host processor creates a task to offload to the storage device).
9. The mass storage device of claim 7, wherein the host processor is to invoke the program code for execution of a task by the mass storage device processor that has a much longer completion time compared to tasks to be executed by the host processor (see BOLKHIVITIN [0011]: offloading tasks to the storage processor allows the tasks to be executed more efficiently, it would take the task longer to execute by the host processor due to the data transfer overhead).
10. The mass storage device of claim 1, wherein the mass storage device processor has a same memory access granularity as the host processor (see BAE [0055]: the chunk size accessed by an external device, such as the host, and the processor in the storage device is the same).
11. BAE discloses A computing system, comprising: a host processor with a plurality of general purpose processing cores (see [0033]: host device with a central processing unit; [0034]: homogeneous or heterogeneous multi-core processor); a main memory controller to manage access to a primary main memory (see [0036]: host main memory); and a mass storage device coupled to a host processor (see [0038]-[0039]: storage device couped with the host device over the interface circuit) including: a non volatile storage media (see [0039]: storage device includes an SSD and stores data regardless of whether power is supplied – this is considered non-volatile media); a local memory coupled to the non volatile storage media (see [0049]: buffer), to local memory to be cache coherent with the primary main memory (see [0063]: the buffer is mapped to host virtual address space, access to the buffer is through the base address register, therefore all access to the buffer will retrieve a coherent version of the data, the data is physically stored in one memory and the buffer is mapped to host virtual address space); and a mass storage device processor (see [0041]: in-storage compute block to process data; [0048]: in-storage compute block can be a processor) to execute code as an additional processing core of the host processor (see BOLKHIVITIN below), wherein the mass storage device processor is to execute instructions out of the local memory (see [0072]: working memory to store data for driving the SSD controller, firmware loaded into the working memory to be executed by the processor), wherein the mass storage device processor is allocated main memory address space for contents of the local memory (see [0046]: buffer of the SSD is mapped to host virtual address space), and wherein operation of the mass storage device processor is compatible with the host processor from a code execution perspective (see BOLKHIVITIN below).
BOLKHIVITIN discloses the following limitations that are not taught by BAE: a mass storage device processor to execute code as an additional processing core of the host processor (see [0041]: host offloads processing tasks to the storage device; [0042]: source code from the host is sent to the storage device processor) wherein operation of the mass storage device processor is compatible with the host processor from a code execution perspective (see [0046]: the processing procedure is sent from the host to the storage device in source code form; [0052]: compiler is unnecessary when the source code is sent directly to the storage device). The host can send the processing procedure in byte code format or source code format. The configuration of the storage device will determine which format will provide the best performance. Using a source code format is a matter of design choice. When source code format is used, the execution of the host processor and storage processor are considered compatible from a code execution perspective since the storage processor can execute the source code sent from the host processor. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify BAE to have the storage processor execute code, as disclosed by BOLKHIVITIN. One of ordinary skill in the art would have been motivated to make such a modification to offload processing from the host and configure the processing procedure that provides the best performance, as taught by BOLKHIVITIN. BAE and BOLKHIVITIN are analogous/in the same field of endeavor as both references are as both references are directed to processing data within a storage device.
12. The computing system of claim 11, wherein the mass storage device processor has a same instruction set architecture as the host processor (see BOLKHIVITIN [0052]: when source code is sent for execution, it is clear the storage processor uses the same instruction set architecture since the storage processor can execute the same source code that can be executed by the host processor).
16. The computing system of claim 11, wherein the non volatile storage media includes any of: a flash memory; solid state storage; a hard disk drive; or a non volatile random access memory (see BAE [0039]: SSD).
17. The computing system of claim 11, wherein the non volatile storage media is to store a data set for execution by the mass storage device processor, based on program code stored in the non volatile storage media (see BAE [0085]: data is retrieved from the non-volatile memory and stored in the buffer, the in-storage computing block processes the data stored in the buffer).
18. The computing system of claim 17, wherein a thread of the host processor is to invoke the program code for execution by the mass storage device processor (see BOLKHIVITIN [0041]: host processor creates a task to offload to the storage device).
19. The computing system of claim 17, wherein the host processor is to invoke the program code for execution of a task by the mass storage device processor that has a much longer completion time compared to tasks to be executed by the host processor (see BOLKHIVITIN [0011]: offloading tasks to the storage processor allows the tasks to be executed more efficiently, it would take the task longer to execute by the host processor due to the data transfer overhead).
20. The computing system of claim 11, wherein the mass storage device processor has a same memory access granularity as the host processor (see BAE [0055]: the chunk size accessed by an external device, such as the host, and the processor in the storage device is the same).
Allowable Subject Matter
Claims 3-5 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the state of the art fails to anticipate, or render obvious, “… the mass storage device processor comprises cache coherency logic circuitry to maintain cache coherency of the local memory with the main memory.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MESNIER [2022/0188028] discloses a host offloading a workload to a storage device. The host generates a compute offload command that is send to a storage device. The command includes a block-based compute descriptor that is sent to the controller. The controller parses the command and executes the offload operation. [Pages 2-4]
LI [2021/0278998]: discloses a storage controller to allow a host to offload processing operations to the storage device. The storage device includes a processor and local memory for in-storage computing. [0046]-[0057]
SONG [10,565,123] discloses data compute operations performed by an SSD controller. [Columns 5-6]
“Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics”: discloses an SSD with a quad core ARM processor executing a Linux operating system to perform processing within the storage device. A DRAM memory is used as a working memory in the SSD. User tasks are offloaded to the accelerator in the SSD.
“Enabling cost-effective data processing with smart SSD”: discloses offloading I/O tasks from a host to an SSD.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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