DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/2026 has been entered.
Response to Amendment
Claims 1-20 are amended. Claims 21-23 are added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “a amplifier” in line 3 of the claim. This appears to mean “an amplifier”. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: Claim 2 recites the limitation “the and the first amplifier” in line 2 of the claim. This appears to mean “and the first amplifier”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wibben et al. U.S. Patent No. 9,285,812 (hereinafter “Wibben”) and further in view of Eckert et al. U.S. Patent No. 6,525,604 (hereinafter “Eckert”).
Regarding claim 1, Wibben teaches a circuit (refer to fig.2), comprising: a power converter (i.e. Buck regulator 10’)(fig.2) including: an amplifier (i.e. error amplifier 42)(fig.2) having an amplifier input (refer to signal 58)(fig.2) and an amplifier output (refer to COMP signal 84)(fig.2); a comparator (i.e. comparator 44)(fig.2) having an input coupled to the amplifier output (implicit) and configurable to provide a modulated signal (refer to comparator output signal 44a) responsive to a first voltage (refer to COMP signal 84)(fig.2) at the input of the comparator (implicit); however, Wibben does not teach circuitry coupled between the amplifier input and the amplifier output, the circuitry configurable to, responsive to the first voltage exceeding a threshold, set a second voltage at the amplifier input responsive to the first voltage. However, Eckert teaches circuitry (i.e. threshold value switches ST2 and ST3)(fig.3) coupled between the amplifier input (refer to input signal SI)(fig.3) and the amplifier output (refer to output of differential amplifier D)(fig.3), the circuitry configurable to, responsive to the first voltage exceeding a threshold (refer to abstract), set a second voltage at the amplifier input responsive to the first voltage (implicit)(refer to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Wibben to include the circuitry of Eckert to provide the advantage of preventing overloading the comparator, thereby preventing damage and/or erroneous signals (refer to Eckert abstract).
Regarding claim 7, Wibben and Eckert teach the circuit of claim 1, wherein the input of the comparator is a first input of the comparator (implicit)(refer to Wibben comparator 44)(fig.2), and the comparator has a second input coupled to a ramp generator source terminal (refer to Oscillator 46 and Ramp 46a)(fig.2).
Regarding claim 8, Wibben and Eckert teach the circuit of claim 7, wherein the ramp generator source terminal is coupled to a ramp generator source configurable to provide a sawtooth waveform (i.e. Wibben Ramp 46a)(fig.2).
Regarding claim 21, Wibben and Eckert teach the circuit of claim 1, wherein the power converter is a buck converter (i.e. Buck regulator 10’)(fig.2), and the first voltage exceeding the threshold indicates at least one of: a difference between an output voltage and an input voltage of the buck converter being within a range, or a duty cycle of the modulated signal reaching a maximum value (implicit)(refer to Eckert abstract).
Allowable Subject Matter
Claims 2-6, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 2-6, 9, and 10 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 2, especially wherein the amplifier is a first amplifier, the amplifier input is a first amplifier input, the and the first amplifier has a second amplifier input coupled to a first reference source; and wherein the circuitry includes: a second amplifier having third and fourth amplifier inputs and a second amplifier output, wherein the third amplifier input is coupled to a second reference source; a first switch coupled between a current source and a ground terminal, and having a first switch control terminal coupled to the second amplifier output, the first switch coupled to the first input of the first amplifier; a third amplifier having fifth and sixth amplifier inputs and a third amplifier output, wherein the fifth amplifier input is coupled to the first amplifier output, and the sixth amplifier input is coupled to a third reference source that at least partially sets the threshold; a second switch having first and second switch terminals and a second switch control terminal, wherein the first switch terminal is coupled to the fifth amplifier input, and the second switch control terminal is coupled to the third amplifier output; a current mirror having a current mirror input and a current mirror output, wherein the current mirror input is coupled to the second switch terminal, and the current mirror output is coupled to the fourth amplifier input; and a fourth amplifier having seventh and eighth amplifier inputs and a fourth amplifier output, wherein the seventh amplifier input is coupled to a first inductor terminal, and the eighth amplifier input is coupled to a second inductor terminal, and the fourth amplifier output is coupled to the first amplifier output. Claims 3-6, 9, and 10 are indicated as containing allowable subject matter based on their dependency on claim 2.
Claims 11-20, 22, and 23 are allowed.
The following is an examiner’s statement of reasons for allowance: Claims 11-20, 22, and 23 are allowable because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 11, especially a first transistor having first and second current terminals and a first transistor control terminal, wherein the second current terminal is coupled to the first transistor control terminal; a second transistor having third and fourth current terminals and a second transistor control terminal, wherein the third current terminal is coupled to the first current terminal, and the second transistor control terminal is coupled to the first transistor control terminal; wherein the second amplifier input is coupled to the fourth current terminal; a third transistor coupled between the second switch terminal and the ground terminal, and having a third transistor control terminal coupled to the second switch terminal; and a fourth transistor coupled between the second current terminal and the ground terminal, and having a fourth transistor control terminal coupled to the third transistor control terminal. The closest prior art references of record are Komiya, Kirchner, Chen, Djelassi, and Daniels. Regarding claim 11, Komiya teaches an apparatus (refer to fig.5), comprising a circuit (refer to fig.5) including: a first amplifier (i.e. voltage detector 100)(fig.5) having first and second amplifier inputs (implicit) and a first amplifier output (i.e. d1)(fig.5); a first switch (i.e. switch SW1)(fig.5) coupled between a current source (i.e. constant current source CC)(fig.5) and a ground terminal (implicit), and having a first switch control terminal coupled to the first amplifier output (implicit); a second amplifier (i.e. output control circuit 11)(fig.5) having third and fourth amplifier inputs (implicit) and a second amplifier output (implicit), wherein the third amplifier input is coupled to a second reference source (i.e. Vref2)(fig.5), the fourth amplifier input is coupled to the first switch (implicit)(refer to top non-inverting input of output control circuit 11)(fig.5); a third amplifier (i.e. limiting circuit 12)(fig.5) having fifth and sixth amplifier inputs (implicit) and a third amplifier output (implicit), wherein the fifth amplifier input is coupled to the second amplifier output (implicit)(refer to inverting input of limiting circuit 12)(fig.5), and the sixth amplifier input is coupled to a third reference source (refer to Vlim)(fig.5); however, Komiya does not teach a first transistor having first and second current terminals and a first transistor control terminal, wherein the second current terminal is coupled to the first transistor control terminal; a second transistor having third and fourth current terminals and a second transistor control terminal, wherein the third current terminal is coupled to the first current terminal, and the second transistor control terminal is coupled to the first transistor control terminal; wherein the first amplifier input is coupled to a first reference source, and the second amplifier input is coupled to the fourth current terminal; a second switch having first and second switch terminals and a second switch control terminal, wherein the first switch terminal is coupled to the fifth amplifier input, and the second switch control terminal is coupled to the third amplifier output; a third transistor coupled between the second switch terminal and the ground terminal, and having a third transistor control terminal coupled to the second switch terminal; and a fourth transistor coupled between the second current terminal and the ground terminal, and having a fourth transistor control terminal coupled to the third transistor control terminal. Kirchner teaches wherein the first amplifier input is coupled to a first reference source (refer to VREF)(fig.2); however, Kirchner does not teach a first transistor having first and second current terminals and a first transistor control terminal, wherein the second current terminal is coupled to the first transistor control terminal; a second transistor having third and fourth current terminals and a second transistor control terminal, wherein the third current terminal is coupled to the first current terminal, and the second transistor control terminal is coupled to the first transistor control terminal; wherein the second amplifier input is coupled to the fourth current terminal; a second switch having first and second switch terminals and a second switch control terminal, wherein the first switch terminal is coupled to the fifth amplifier input, and the second switch control terminal is coupled to the third amplifier output; a third transistor coupled between the second switch terminal and the ground terminal, and having a third transistor control terminal coupled to the second switch terminal; and a fourth transistor coupled between the second current terminal and the ground terminal, and having a fourth transistor control terminal coupled to the third transistor control terminal. Chen teaches a second switch (i.e. clamping switch 302)(fig.3) having first and second switch terminals (implicit) and a second switch control terminal (implicit), wherein the first switch terminal is coupled to the fifth amplifier input (refer to non-inverting input of amplifier 301)(fig.3), and the second switch control terminal is coupled to the third amplifier output (implicit)(refer to amplifier 301)(fig.3); however, Chen does not teach a first transistor having first and second current terminals and a first transistor control terminal, wherein the second current terminal is coupled to the first transistor control terminal; a second transistor having third and fourth current terminals and a second transistor control terminal, wherein the third current terminal is coupled to the first current terminal, and the second transistor control terminal is coupled to the first transistor control terminal; wherein the second amplifier input is coupled to the fourth current terminal; a third transistor coupled between the second switch terminal and the ground terminal, and having a third transistor control terminal coupled to the second switch terminal; and a fourth transistor coupled between the second current terminal and the ground terminal, and having a fourth transistor control terminal coupled to the third transistor control terminal. Djelassi (figures 5 and 6) and Daniels (figures 4 and 5) teach similar circuits, however they do not teach a first transistor having first and second current terminals and a first transistor control terminal, wherein the second current terminal is coupled to the first transistor control terminal; a second transistor having third and fourth current terminals and a second transistor control terminal, wherein the third current terminal is coupled to the first current terminal, and the second transistor control terminal is coupled to the first transistor control terminal; wherein the second amplifier input is coupled to the fourth current terminal; a third transistor coupled between the second switch terminal and the ground terminal, and having a third transistor control terminal coupled to the second switch terminal; and a fourth transistor coupled between the second current terminal and the ground terminal, and having a fourth transistor control terminal coupled to the third transistor control terminal. It would not have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Komiya, Kirchner, Chen, Djelassi, and/or Daniels to arrive at the claimed invention. Claims 12-20, 22, and 23 are allowed based on their dependency on claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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