Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/16/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “high-bandwidth” and “low-latency” in claim 6 are relative terms which renders the claim indefinite. The term terms “high-bandwidth” and “low-latency” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Accordingly, the metes and bounds of the recited open interconnect standard would not be known to one of ordinary skill in the art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 10-14, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Haghighat et al. (WO 2020/096639) in view of Wilson et al. US (2002/0178332) and Kirkman (US 6,581,063).
Claim 1 is taught by Haghighat as:
A memory device comprising: a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. Paragraphs 0028 and 0029 show that memory controller 104 includes a translation data structure 162. Paragraph 0032 teaches translation data structure 162 which stored mapping data that relates an OS page number (virtual address) with a mem page number (physical address).
the data arranged in […] a physical memory of the memory device. Paragraphs 0035 and 0036 show that one or more OS pages may be stored to one mem page.
and a controller: Paragraph 0029, memory controller 104.
Haghighat does not expressly teach that the data is arranged in multiple stripes, or that responsive to the data of the virtual page being compressed data, to load information about a second stripe of the compressed data into extra locations in the first stripe, the extra locations being locations in the first stripe different from locations for compressed data of the virtual page
With respect to claim 1, Wilson teaches:
A memory device comprising: a mapping table having an entry location to associate a virtual page with a […] address of a first stripe of data of the virtual page. Figure 1, table 200 containing pointers 220, see paragraph 0018 showing that each chain of compressed data blocks 210 contain the compressed data from a single page of uncompressed data.
the data arranged in multiple stripes in a physical memory of the memory device. Paragraphs 0018 shows that a page of data is stored in a plurality of blocks 210.
responsive to the data of the virtual page being compressed data, to load information about a second stripe of the compressed data into extra locations in the first stripe. Paragraph 26 shows that a page of data is compressed into a number of compressed data blocks 210. Paragraph shows that uncompressed pointer 220 is stored in each compressed data block to create a chain of compressed data blocks 210.
the extra locations being locations in the first stripe different from locations for compressed data of the virtual page. Figure 1 shoes uncompressed pointer 220 separate from compressed data block 210.
As of the effective filing date of the invention, it would have been obvious to combine the chained compressed data storage of Wilson with the memory system of Haghighat.
The motivation for doing so would have been to efficiently use resources such as the memory required for a table specifying the locations of the compressed data, see Wilson paragraph 5.
Wilson paragraph 0022 shows that the pointer 220 of the compressed is read first, allowing the retrieval of the next block. As the pointer 220 stores information about the compressed data, it is metadata of the compressed data. Paragraph 0018 shows that the block 210, of which pointer 220 is part, comprises bits. Paragraph 0018 shows that the pointer is not compressed, while the data 230 is compressed. As the bits storing the pointer are not overwritten, they are reserved.
The combination of Haghighat and Wilson does not expressly teach each stripe having a section for data blocks and a section of extra locations, the section of extra locations being separate from the section for data.
With respect to claim 1, Kirkman teaches a linked list containing data, analogous to the data blocks, (column 1 lines 54 through column 2 line 9) and containing a plurality of linked list data structures 210, 21, 212, analogous to the claimed stripes, containing at least two pointers, analogous to the extra locations, (column 4 line 64 through column 5 line 14). Figure 3 and column 6 lines 15-34 discuss the locations of the the pointers are defined as offsets, and are shown as separate from the data portion of the link.
As of the effective filing date of the application, it would have been obvious to one of ordinary skill in the art to combine the linked list structure of Kirkman with the system of Haghighat and Wilson.
The motivation for doing so would have been to improve multiprocessing performance, see column 3 lines 11-20.
Therefore, it would have been obvious to combine Haghighat, Wilson, and Kirkman to obtain the invention as recited in claims 1-5.
Claim 2 is taught by Haghighat and Wilson as:
The memory device of claim 1, wherein the information about the second stripe includes the physical address of the second stripe. Wilson paragraph shows that uncompressed pointer 220 is stored in each compressed data block to create a chain of compressed data blocks 210. Haghighat paragraph 0036 shows that data locations can be indicated by physical addresses.
Claim 3 is taught by Wilson as:
The memory device of claim 1, wherein the controller is arranged to load information about a third stripe of compressed data into extra locations in the second stripe, the extra locations in the second stripe being locations different from locations for the compressed data of the virtual page. Paragraph 26 shows that a page of data is compressed into a number of compressed data blocks 210. Paragraph shows that uncompressed pointer 220 is stored in each compressed data block to create a chain of compressed data blocks 210. Figure 1 and paragraph 0029 show that there can be a third compressed data block 210 pointed to by the second compressed data block.
Claim 4 is taught by Haghighat and Wilson as:
The memory device of claim 3, wherein the information about the third stripe includes the physical address of the third stripe. Wilson paragraph shows that uncompressed pointer 220 is stored in each compressed data block to create a chain of compressed data blocks 210. Haghighat paragraph 0036 shows that data locations can be indicated by physical addresses.
Claim 5 is taught by Haghighat as:
The memory device of claim 1, wherein the memory device includes a free space manager to make available physical addresses to write data from a host to a memory subsystem of the memory device. Paragraphs 0076 and 0077 shows that a target mem page with available portion may be found and selected by translation module 160.
Claim 7 is taught by Haghighat as:
A method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a read request to the memory device from a host device. Paragraphs 0028 and 0029 show that memory controller 104 includes a translation data structure 162. Paragraph 0032 teaches translation data structure 0032 which stored mapping data that relates an OS page number (virtual address) with a mem page number (physical address). Paragraph 0098 shows that the processor 102 may initiate read operations, and translation module 160 uses translation data structure 162 to determine the current storage location of the target page.
Haghighat does not expressly teach accessing a chain of compressed stripes of data as recited in claim 7.
With respect to claim 7, Wilson teaches:
A method of operating a memory device, the method comprising: accessing an indirection table based on a read request to the memory device from a host device. Paragraph 0021 shows that the table 200 of pointers 210 is accessed to obtain the location of the head of the chain of compressed data blocks 210.
reading a first stripe of multiple stripes of compressed data from a physical memory of the memory device, the multiple stripes of compressed data corresponding to the read request. Paragraph 0022 shows that the head 210a of the chain is fetched. Figure 1 and paragraph 0029 show that there can be a third compressed data block 210 pointed to by the second compressed data block.
the first stripe read from the physical memory at a […] address listed in the indirection table corresponding to the virtual address. Paragraph 0022 shows that pointer 220 is used to fetch the head of the chain of compressed data blocks.
reading, from reserved bits of the first stripe for storing metadata of the compressed data, a […] address of a next stripe of the multiple stripes of compressed data. Paragraph 0022 shows that pointer 220 in the compressed data block is read first to support the retrieval of the next block 210. Paragraph 0022 shows that the pointer 220 of the compressed is read first, allowing the retrieval of the next block. As the pointer 220 stores information about the compressed data, it is metadata of the compressed data. Paragraph 0018 shows that the block 210, of which pointer 220 is part, comprises bits. Paragraph 0018 shows that the pointer is not compressed, while the data 230 is compressed. As the bits storing the pointer are not overwritten, they are reserved.
reading the next stripe of compressed data from the physical memory corresponding to the […] address of the next stripe, including reading a physical address of a subsequent stripe of the multiple stripes of compressed data. Paragraph 0022 shows that next block 210 is read, figure 2 shows that next block 210 also contains a pointer to a subsequent compressed data block.
sequentially reading remaining stripes of the multiple stripes, beyond the next stripe, each of the remaining stripes read from the physical memory at a […] address obtained while reading a previous stripe in the sequential reading. Paragraphs 0023 and 0024 show that if there are more compressed blocks in the chain, they are read in the same way until all blocks in the chain have been read, and that that reading is performed while the decompression of the previous stripe is being performed, which is part of the reading process.
and uncompressing the compressed data read from the multiple stripes. Paragraph 0025 shows that all compressed blocks 210 are decompressed.
As of the effective filing date of the invention, it would have been obvious to combine the chained compressed data storage of Wilson with the memory system of Haghighat.
The motivation for doing so would have been to efficiently use resources such as the memory required for a table specifying the locations of the compressed data, see Wilson paragraph 5.
With respect to claim 7, Kirkman teaches reading a linked list containing data, analogous to the data blocks, (column 1 lines 54 through column 2 line 9) and containing a plurality of linked list data structures 210, 21, 212, analogous to the claimed stripes, containing at least two pointers, analogous to the extra locations, (column 4 line 64 through column 5 line 14). Figure 3 and column 6 lines 15-34 discuss the locations of the the pointers are defined as offsets, and are shown as separate from the data portion of the link.
As of the effective filing date of the application, it would have been obvious to one of ordinary skill in the art to combine the linked list structure of Kirkman with the system of Haghighat and Wilson.
The motivation for doing so would have been to improve multiprocessing performance, see column 3 lines 11-20.
Therefore, it would have been obvious to combine Haghighat, Wilson, and Kirkman to obtain the invention as recited in claims 7 and 10-13.
Claim 10 is taught by Wilson as:
The method of claim 7, wherein the method includes uncompressing the compressed data after all the compressed data of the multiple stripes of compressed data is read from the physical memory of the memory device. Paragraphs 0024 and 0025 show that the decompression is performed for each compressed data block while the subsequent data block is fetched, however the decompression is not complete until after the last block is read, accordingly the complete uncompressing happens after all of the compressed data is read.
Claim 11 is taught by Haghighat and Wilson as:
The method of claim 7, wherein the method includes copying uncompressed data, generated after reading the multiple stripes from the physical memory, to one or more caches of the memory device or to one or more read buffers of the memory device. Haghighat paragraph 0082 shows that data can be read into a cache. Wilson paragraph 00345 shows that the uncompressed data is returned after reading all compressed data blocks.
Claim 12 is taught by Haghighat as:
The method of claim 7, wherein accessing the indirection table includes loading the indirection table if the indirection table is not cached. Paragraph 30 shows that translation cache 166 stores a portion of the translation data structure 162 analogous to a TLB and a page table.
Claim 13 is taught by Haghighat as:
The method of claim 7, wherein each stripe of the multiple stripes has a size of 64 bytes. Paragraph 0040 shows that64 bytes is a known size for a stored data portion in a computer system.
Claim 14 is taught by Haghighat as:
A method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a write request to the memory device from a host device. Paragraphs 0028 and 0029 show that memory controller 104 includes a translation data structure 162. Paragraph 0032 teaches translation data structure 0032 which stored mapping data that relates an OS page number (virtual address) with a mem page number (physical address). Paragraph 0082 shows that the processor 102 may initiate write operations, and paragraph 0083translation module 160 uses translation data structure 162 to determine the current storage location of the target page.
obtaining physical addresses of a physical memory from a free space manager of the memory device based on size of the compressed data. Paragraph 0088 shows that a search is made to identify at least one mem page that has sufficient available storage space to store the target OS page.
Haghighat does not expressly teach accessing a chain of compressed stripes of data as recited in claim 14.
With respect to claim 14, Wilson teaches:
A method of operating a memory device, the method comprising: accessing an indirection table based on a write request to the memory device from a host device. Paragraph 0028 shows that a pointer 220 to the head 210a of the chain is stored in the table 200.
compressing data of a user page size corresponding to the write request, generating compressed data. Paragraph 0026 shows that a page of data is compressed into a number of compressed data blocks 210.
the […] addresses defining locations of multiple stripes to store the compressed data in the physical memory. Figure 1 shows a plurality of compressed data blocks.
updating the indirection table with a first physical address of the physical addresses, the first physical address corresponding to a first stripe of the compressed data. Paragraph 0028 shows that a pointer 220 to the head 210a of the chain is stored in the table 200.
writing a second physical address of the physical addresses into bits of the first stripe in the physical memory, the bits reserved for storing metadata of the compressed data, the second physical address corresponding to a second stripe of the compressed data. Paragraph 0027 shows that an uncompressed pointer 220 is stored in each compressed data block 210. Paragraph 0022 shows that the pointer 220 of the compressed is read first, allowing the retrieval of the next block. As the pointer 220 stores information about the compressed data, it is metadata of the compressed data. Paragraph 0018 shows that the block 210, of which pointer 220 is part, comprises bits. Paragraph 0018 shows that the pointer is not compressed, while the data 230 is compressed. As the bits storing the pointer are not overwritten, they are reserved.
sequentially writing remaining stripes of the multiple stripes to the physical memory, beyond the second stripe, each of the remaining stripes containing a physical address at which to write a subsequent stripe in the sequential writing until writing a last stripe of the compressed data of a virtual page corresponding to the virtual address. Paragraphs 0026 and 0027 show that the process of compressing data blocks and adding to them to a chain continues for all of the compressed data blocks, see figure 4.
As of the effective filing date of the invention, it would have been obvious to combine the chained compressed data storage of Wilson with the memory system of Haghighat.
The motivation for doing so would have been to efficiently use resources such as the memory required for a table specifying the locations of the compressed data, see Wilson paragraph 5.
With respect to claim 14, Kirkman teaches a linked list containing data, analogous to the data blocks, (column 1 lines 54 through column 2 line 9) and containing a plurality of linked list data structures 210, 21, 212, analogous to the claimed stripes, containing at least two pointers, analogous to the extra locations, (column 4 line 64 through column 5 line 14). Figure 3 and column 6 lines 15-34 discuss the locations of the the pointers are defined as offsets, and are shown as separate from the data portion of the link.
As of the effective filing date of the application, it would have been obvious to one of ordinary skill in the art to combine the linked list structure of Kirkman with the system of Haghighat and Wilson.
The motivation for doing so would have been to improve multiprocessing performance, see column 3 lines 11-20.
Therefore, it would have been obvious to combine Haghighat, Wilson, and Kirkman to obtain the invention as recited in claims 14, 16, 17, 19, and 20.
Claim 16 is taught by Wilson as:
The method of claim 14, wherein writing the first stripe, the second stripe, and the remaining stripes with a physical address of a subsequent stripe of the compressed data being written includes writing the physical address in each stripe in reserved bit locations in each stripe. Paragraph 0027 shows that an uncompressed pointer 220 is stored in each compressed data block 210, shown in figure 2 to be separate locations.
Claim 17 is taught by Haghighat as:
The method of claim 14, wherein accessing the indirection table includes loading the indirection table for processing. Paragraph 30 shows that translation cache 166 stores a portion of the translation data structure 162 analogous to a TLB and a page table.
Claim 19 is taught by Haghighat as:
The method of claim 14, wherein accessing the indirection table includes accessing the indirection table in a cache, the indirection table including a first physical address corresponding to the virtual address. Paragraph 30 shows that translation cache 166 stores a portion of the translation data structure 162 analogous to a TLB and a page table.
Claim 20 is taught by Haghighat as:
The method of claim 14, wherein the user page size is 4 KB. Paragraph 0024 shows that a page may be 4 KB.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Haghighat et al. (WO 2020/096639) in view of Wilson et al. US (2002/0178332) and Kirkman (US 6,581,063) as applied to claim 1 above, and further in view of Synopsys (An Introduction to the CXL Device Types).
Claim 6 is taught by the combination of Haghighat, Wilson, and Kirkman as shown supra with respect to claim 1.
The combination of Haghighat, Wilson, and Kirkman do not expressly teach the memory device is operable in accordance with input/output and memory protocols of an open interconnect standard configured for high-bandwidth, low-latency connectivity.
With respect to claim 6, Synopsys teaches: wherein the memory device is a compute express link (CXL) type 3 memory device. At the bottom of page 1, it is shown that a CXL type 3 device exists, which is an open interconnect standard configured for high-bandwidth, low-latency connectivity.
As of the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to implement the memory device of Haghighat, Wilson, and Kirkman as a CXL type 3 device.
The motivation for doing so would have been that CXL acts as a high-preforming I/O interconnect system, see the second paragraph beginning on page 2 of Synopsys.
Therefore, it would have been obvious to combine Haghighat, Wilson, and Kirkman with Synopsys to obtain the invention as recited in claim 6.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Haghighat et al. (WO 2020/096639) in view of Wilson et al. US (2002/0178332) and Kirkman (US 6,581,063) as applied to claim 1 above, and further in view of Sallese et al. (US 11,036,427).
Claim 8 is taught by the combination of Haghighat, Wilson, and Kirkman as shown supra with respect to claim 7.
The combination of Haghighat, Wilson, and Kirkman does not expressly teach the method includes placing additional read requests for data corresponding to the virtual address in a progress list.
With respect to claim 7, Sallese teaches: wherein the method includes placing additional read requests for data corresponding to the virtual address in a progress list. Discussing method 500 shown in figure 5, column 12 line 26 through column 13 line 21, a read to a logical address which is currently undergoing a RMW operation can be held for a predetermined amount of time until the pending RMW operation is completed.
At the time of the invention, it would have been obvious to one of ordinary skill in the art to combine the read holding of Sallese with the memory system of Haghighat, Wilson, and Kirkman.
The motivation for doing so would have been to ensure coherency is maintained for read modify write operations, Sallese column 15 lines 42-45.
Therefore, it would have been obvious to combine Haghighat, Wilson, and Kirkman with Sallese to obtain the invention as recited in claim 8.
Allowable Subject Matter
Claims 9, 15, and 18 are allowed.
Response to Arguments
Applicant’s arguments, page 8 of the remarks submitted 12/22/2025, with respect to the rejection(s) of claim(s) 6 under 35 U.S.C. 112(b) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as presented supra.
Applicant’s arguments, see page 9 of the remarks submitted 12/22/2025, with respect to the rejection(s) of claim(s) Claims 1-5, 7, 10-14, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Haghighat et al. (WO 2020/096639) in view of Wilson et al. US (2002/0178332) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Haghighat et al. (WO 2020/096639) in view of Wilson et al. US (2002/0178332) and Kirkman (US 6,581,063).
In the last paragraph beginning on page 9 of the remarks, Applicant argues “As noted in paragraphs [0007] and [0023], Wilson’s pointers are located in data blocks. Wilson does not teach a stripe structured with a section of data blocks and a separate section of extra locations.” Paragraph 0018 plainly states “Whereas the data 230 is in the blocks 210 are compressed, the pointer 220 itself is not.” Accordingly, Wilson plainly shows the data being different from the pointer. Wilson uses the term “data block” to describe the data structure of a node in a linked list containing the data of the node and the pointer to the next node. Wilson’s data block is analogous to the stripe of the claimed invention. Wilson does not however, teach plural locations different from the data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached Monday-Friday, 8:00 AM to 4:00 PM.
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/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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