Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 07/24/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, i.e. including a level-shifter coupled to a differential amplifier.
Appropriate correction is required.
Claim Objections
Claims 1, 4, 8, and 10 are objected to because of the following informalities: Regarding claim 1, in line 14, “the level-shifted voltage” appears that it should read as “a level-shifted voltage”. Regarding claim 4, in line 3-4, “the voltage” appears that it should read as “the voltage at the output node of the differential amplifier circuit”. Regarding claim 8, in line 5-6, “the voltage” appears that it should read as “the voltage at the output node of the differential amplifier circuit”. Regarding claim 10, in line 9, “the output node” appears that it should read as “the output node of the differential amplifier circuit”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 6, 11, and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Noda (US Patent Application Publication US 2009/0128116 A1). Regarding claim 1, Noda discloses (see Fig. 1 and Fig. 3) a semiconductor circuit device (see controller comprising 3, 4, and 5) that is used for a switching regulator (see switching regulator 1) that regulates an input voltage (Vin) using a switching device (M1, M2) and an inductor (L1) and outputs an output voltage (Vout), the semiconductor circuit device comprising: a current detecting circuit (4) that converts an inductor current (iL) flowing through the inductor into a voltage and outputs the voltage as a current detection voltage (4 outputs voltage of Vi); a differential amplifier circuit (comprising 21 and 24, M25 of Fig. 3) that includes a MOS transistor (M25) provided between a power supply node (GND) and an output node (top-side node of M25) and amplifies a difference between a voltage corresponding to the output voltage (Vfb) and a reference voltage (Vref); a level shifter (comprising M26, 25 of Fig. 3) that level-shifts a voltage at the output node of the differential amplifier circuit (voltage at top-side node of M25) to a low potential side (Ve) and outputs the level-shifted voltage (M26 and 25 outputs Ve); and a comparing circuit (5) that compares the current detection voltage with the level-shifted voltage (5 compares Vi with Ve) and outputs a switching signal for the switching device (Rst).
Regarding claim 2, Noda discloses (see Fig. 1 and Fig. 3) wherein the level shifter is a source follower circuit (see [0070] “because the NMOS transistor 26 forms a source follower circuit”).
Regarding claim 3, Noda discloses (see Fig. 1 and Fig. 3) wherein the source follower circuit includes an N-type MOS transistor (M26 is an N-MOS) having a gate (gate of M26) to which the voltage at the output node of the differential amplifier circuit is input (the voltage of the top-side node of M25 is input to the gate of M26), and a source (source of M26) from which the level-shifted voltage is output (source of M26 outputs Ve), and a resistor or a current source (25 is a current source providing ib3) provided between the source and a low-potential-side power supply node (GND).
Regarding claim 6, Noda discloses (see Fig. 1 and Fig. 3) wherein a gain of the level shifter is 0 dB (see [0070] “because the NMOS transistor 26 forms a source follower circuit, a gain thereof is identical or similar to 1.”, Examiner’s Note: a gain of 1 is equivalent to a gain of 0 dB).
Regarding claim 11, Noda discloses (see Fig. 1 and Fig. 3) further comprising a phase compensation circuit (comprising Rf1, Cf1) coupled to the output node of the differential amplifier circuit, wherein the phase compensation circuit includes a resistor (Rf1) and a first capacitor (Cf1) that are coupled in series between the output node of the differential amplifier circuit and a low-potential-side power supply node (GND; Rf1 and Cf1 are coupled in series between the top-side node of M25 and GND).
Regarding claim 12, Noda discloses (see Fig. 1 and Fig. 3) a switching regulator (1) comprising: the semiconductor circuit device according to claim 1; and the inductor (L1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Noda in view of Sheehan (R. Sheehan, “Understanding and applying current-mode control theory,” TI SNVA555, Texas Instruments, 2007). Regarding claim 5, Noda discloses (see Fig. 1 and Fig. 3) wherein a gain of the level shifter (see [0070] “because the NMOS transistor 26 forms a source follower circuit, a gain thereof is identical or similar to 1.”, Examiner’s Note: a gain of 1 is equivalent to a gain of 0 dB) is smaller than a gain of a compensator including the differential amplifier circuit (see [0078] “the gain of the differential unit 21 is 10”). Noda does not explicitly disclose wherein the gain of the level shifter is smaller than a gain of a plant including the switching device, the inductor, the current detecting circuit, and the comparing circuit, and smaller than a product of the gain of the plant and the gain of the compensator. However, Sheehan teaches (see Fig. ) the general condition in calculating the gain of a plant (see p. 9 Fig. 6) including the switching device (S1, S2), the inductor (L), the current detecting circuit (Gi), and the comparing circuit (Fm) (see p. 11, where the control to output gain of the plant = 14.3 = 23dB), and calculating the gain of the compensator (see p.13, GeA = 2.7 = 8.5 dB). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor circuit of Noda wherein the gain of the level shifter is smaller than a gain of a plant including the switching device, the inductor, the current detecting circuit, and the comparing circuit, and smaller than a product of the gain of the plant and the gain of the compensator, as taught by the general condition of Sheehan, because it can help provide level shifting to a stable switching regulator without losing stability (the gain of the level shifter of Noda is 1, which would be smaller than 14.3, and smaller than the product of 14.3 x 2.7 when modified in view of Sheehan), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Noda in view of Henry (US Patent US 6,388,521 B1). Regarding claim 7, Noda does not disclose wherein the differential amplifier circuit includes a first output-stage transistor that is provided between a first power supply node and a first node and outputs a current, and a second output-stage transistor that is provided between the first node and the output node and has a gate to which a first bias voltage is input. However, Henry teaches (see Fig. 3) wherein the differential amplifier circuit (comprising M10’, M11’, M30’, M33’, M31’, M34’) includes a first output-stage transistor (M11’) that is provided between a first power supply node (bottom-side node of M11’) and a first node (top-side node of M11’) and outputs a current (current output to M31’), and a second output-stage transistor (M31’) that is provided between the first node and the output node (bottom-side node of M31’) and has a gate (gate of M31’) to which a first bias voltage is input (CASCODE BIAS POINT). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor circuit of Noda wherein the differential amplifier circuit includes a first output-stage transistor that is provided between a first power supply node and a first node and outputs a current, and a second output-stage transistor that is provided between the first node and the output node and has a gate to which a first bias voltage is input, as taught by Henry, because it can help implement a differential amplifier circuit using CMOS technology.
Allowable Subject Matter
Claims 4, and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 4, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein an amount by which the level shifter level-shifts the voltage is equal to or greater than an overdrive voltage when a transistor included in an output stage of the differential amplifier circuit operates in a saturated state.”. Regarding Claim 8, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first power supply node is a low-potential-side power supply node, and an amount by which the level shifter level-shifts the voltage is equal to or greater than an overdrive voltage when the first output-stage transistor and the second output-stage transistor operate in a saturated state.”.
Claims 9 and 10 are objected due to their dependency on claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication 2023/0152869 A1 discloses a differential amplifier with output level shifting. US Patent Application Publication 2015/0357914 A1 discloses a differential amplifier for a buck converter with output level shifting.
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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