DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 12, 2024, September 18, 2025 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-14) in the reply filed on September 17, 2026 is acknowledged.
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 17, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "corresponding memory arrays" in line 3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “corresponding memory arrays of the one or more memory arrays”.
Claim 3 recites the limitation "corresponding memory arrays" in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “corresponding memory arrays of the one or more memory arrays”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 2020/0266207). Claim 1, Liu discloses (Figs 2 and. 5B) a semiconductor device assembly, comprising (Fig. 5B): a substrate (510, second substrate, Para [0076]); a plurality of functional devices (530, array interconnection layer, Para [0065]) disposed above the substrate (530 is above 510); and a memory device (NAND flash memory device above 570, Para [0068], hereinafter “mem”) disposed above the plurality of functional devices (mem is above 530), the memory device including: one or more memory arrays (580, conductor/dielectric pairs forms array device, Para [0068]), a plurality of first vertical electrical connectors (514, slit structure filled with conductive material, Para [0070]) having a first diameter (514 has a diameter determined by horizontal length in Fig. 5A, hereinafter “d1”) and extending vertically (514 extends in Y vertical direction) , and a plurality of second vertical electrical connectors (526, through array contact, Para [0067]) having a second diameter (526 has a diameter determined by horizontal length in Fig. 5A, hereinafter “d2”) and extending vertically (526 extends in Y vertical direction), wherein the second diameter is greater than the first diameter (d2 is greater than d1 as seen in Fig. 5A). Claim 8, Liu discloses (Figs 2 and. 5A) the semiconductor device assembly of claim 1, wherein each of the plurality of second vertical electrical connectors (526) has a cross-sectional shape with two or more arcs (Fig. 2 shows the shape of corresponding TACs 226 which can be considered two arcs forming a circle).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 10, and 14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Parekh (US 2023/0143455).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1, Parekh discloses (Fig. 1) a semiconductor device assembly, comprising: a substrate (110, semiconductive base structure, Para [0065]); a plurality of functional devices (106, first interconnect region, Para [0079]) disposed above the substrate (106 is disposed above 110); and a memory device (104, device formed by memory array region, Para [0029]) disposed above the plurality of functional devices (104 is above 106), the memory device including: one or more memory arrays (104), a plurality of first vertical electrical connectors (128, cell pillar structures with polysilicon pillar, Para [0041]) having a first diameter (diameter corresponds to lateral width of 128 in Fig. 1, hereinafter “d1”) and extending vertically (128 extends in vertical Z-direction), and a plurality of second vertical electrical connectors (126, deep contact structures, Para [0040]) having a second diameter (diameter corresponds to lateral width of 126 in Fig. 1, hereinafter “d2”) and extending vertically (126 extends in vertical Z-direction), wherein the second diameter is greater than the first diameter (d2 is greater than d1 as shown in Fig. 1). Claim 7, Parekh discloses (Fig. 1) the semiconductor device assembly of claim 1, wherein the plurality of second vertical electrical connectors (126) extend at least partially through the one or more memory array (126 extends through 124 of array 104).
Claim 10, Parekh discloses (see annotated Fig. 1 below) a semiconductor apparatus, comprising: a top portion (106, first interconnect region, Para [0050]) including a first wafer-to-wafer bond pad (bond1, 146, connected bond pads, Para [0050]) and a second wafer-to-wafer bond pad (bond2, 146, connected bond pads, Para [0050]) configured to interface with one or more external circuits (146s interface with control logic region 102, Para [0050]); a lower portion (108, second interconnect region, Para [0056]) including one or more functional circuits (152/154/156/158, second routing structures/fourth contact structures/conductive pads/fifth contact structures, Para [0058], hereinafter “circuit”) with a first connection point (p1) and a second connection point (p2); a first vertical connector (128, cell pillar structures, Para [0041]) extending vertically (128 extends in vertical direction) and electrically coupling the first connection point to the first wafer-to-wafer bond pad (128 couples p1 to bond1), wherein the first vertical connector has a first lateral dimension (width of 128 is first lateral dimension, hereinafter “lat1”); and a second vertical connector (126, deep contact structure, Para [0047]) extending vertically (126 extends vertically) and electrically coupling the second connection point to the second wafer-to-wafer bond pad (126 couples p2 to bond2), wherein the second vertical connector has a second lateral dimension (width of 126 is the second lateral dimension, hereinafter “lat2”) that is greater than the first lateral dimension (as can be seen in Fig. 1, lat2 is greater than lat1).
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Claim 14, Parekh discloses (see annotated Fig. 1 above) the semiconductor apparatus of claim 10, wherein the second vertical connector (126) has a cross-sectional shape with two or more arcs (cross-section slice of top of 126 is a circle shape which can be considered a combination of two arcs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parekh (US 2023/0143455) as applied to claims 1 and 10 above, and further in view of Lee (US 2012/0285481)
Claim 6, Parekh discloses (see annotated Fig. 1 above) the semiconductor device assembly of claim 1, wherein the plurality of second vertical electrical connectors (deep contact structure 126) have a length (126 has a length). Parekh does not explicitly disclose wherein the second diameter of the second vertical electrical connectors is associated with the length to form an aspect ratio of the second vertical electrical connectors being 10:1 or less. However, Lee discloses forming deep contact with an aspect ratio of 4:1 or smaller (Para [0010]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the aspect ratio of Lee to the deep contact structure of Parekh as an aspect ratio 4:1 or smaller will result in a simpler cleaning process during manufacturing (Lee, Para [0010]). Claim 13, Parekh discloses (see annotated Fig. 1 above) the semiconductor apparatus of claim 10. Parekh does not explicitly disclose wherein the second vertical connector has an aspect ratio being 10:1 or less. However, Lee discloses forming deep contact with an aspect ratio of 4:1 or smaller (Para [0010]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the aspect ratio of Lee to the deep contact structure of Parekh as an aspect ratio 4:1 or smaller will result in a simpler cleaning process during manufacturing (Lee, Para [0010]).
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejections above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Liu (US 2020/0266207), Parekh (US 2023/0143455), Lee (US 2012/0285481), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 2 (from which claim 3 depends), wherein at least one of the plurality of second vertical electrical connectors is connected to a corresponding SRC.
Claims 4-5 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejections above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Liu (US 2020/0266207), Parekh (US 2023/0143455), Lee (US 2012/0285481), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4, wherein the second diameter of the plurality of second vertical electrical connectors is greater than the first diameter of the plurality of first vertical electrical connectors by a factor of 2 or greater.
Regarding Claim 5, wherein the first diameter of the plurality of first vertical electrical connectors is 900 nm or less, and wherein the second diameter of the plurality of second vertical electrical connectors is 1.5 µm or greater.
Regarding Claim 11, wherein the second lateral dimension of the second vertical connector is greater than the first lateral dimension of the first vertical connector by a factor of 2 or greater.
Regarding Claim 12, wherein the first lateral dimension of the first vertical connector is 900 nm or less, and wherein the second lateral dimension of the second vertical connector is 1.5 µm or greater.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
