A WAKE-UP SIGNAL WITH A GAP DURATION

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted, IDS - 01/02/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1- 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by D'Addato, Matteo. "Architectures and circuits for ultra-low-power integrated wake-up radios." (2023). (Year: 2023) hereinafter “Matteo-Addato”. Regarding Claim 1, Matteo-Addato discloses, ‘An apparatus for wireless communication at a user equipment (UE), comprising: one or more memories’ (A Wake-up Receiver (WuRx) architectures in Fig. 3.1, page-35 and a Gated oscillator clock and data recovery circuit in Fig. 3.4 in page-37 The WuRx operate ultra-low power receiver includes memory/processor, page-34 [0008]. ); And discloses, ‘and one or more processors, coupled to the one or more memories, configured to cause the UE to: receive a wake-up signal that includes at least a clock acquisition section, a data section, and a gap duration that is positioned between the clock acquisition section and the data section’ (WuRX, oversampling techniques are typically used in order to overcome phase misalignment between received data and internal clock, section-3.2.2, page-35 [0008]. Disclosure, Gate Oscillator clock and data recovery circuit in Fig. 3.4 and disclosure exemplified a prototype receiver h/w design in Fig. 4.8 page-59. And, the gate oscillator eliminates the effects of phase/frequency misalignment uses relaxation oscillator ultra-low-power consumption that reduces excessive power consumption, section-3.2.2, page-35 [0019]. ); PNG media_image1.png 820 1248 media_image1.png Greyscale In Figure 3.4, the gate-oscillator clock and data recovery-circuit composed three main blocks: a) a Delay block (DB), b) an Edge Detector (EXNOR) and c) the Gated Oscillator, plus an additional biasing block. τd being the time delay, page-36 to 37. The operation of the entire CDR circuit is described by the waveforms in Figure 3.5, where Tb is the bit time. For the correct operation of the CDR-circuit. To have a non-null duration of the clock high phase Tb/2−τd > 0, must be guaranteed, which sets an upper value for τd. Page-37 to 38. PNG media_image2.png 666 614 media_image2.png Greyscale And discloses, ‘and configure, within the gap duration, receiver hardware using information that is based at least in part on the clock acquisition section.’ (In Fig. 3.4 gate oscillator circuit includes the clock acquisition.) Regarding Claim 2, ‘The apparatus of claim 1’ (disclosed above), And discloses, ‘wherein the one or more processors, to cause the UE to configure the receiver hardware, are configured to cause the UE to: configure a cutoff frequency of a low-pass filter.’ (In Figure 4.2 in page-48 and the output voltage VOUT_AMP is a low-pass filtered version of the RF input envelope, section 4.1.1, page-46. And, in Fig. 4.1 illustrates the block diagram of WuRx includes ED component and VOUT_AMP, page-47.) Regarding Claim 3, ‘The apparatus of claim 2’ (disclosed above), And discloses, ‘wherein the information comprises at least one of: a symbol duration, or a chip length.’ (As part of the clock and data recovery operation, a phase error estimated. And, constraints on maximum number of equal consecutive bits (Nm) is not total number of transmitted bits, page-37. And Nm is calculated sampling is done considering the high frequency and low frequency compared to target bit-time. For the high values of Nm, an additional calibration circuit is required, page-38. The WuRx uses on-off-Keying modulated input, chapter-4, page-45, First Prototype. ) Regarding Claim 4, ‘he apparatus of claim 2’ (disclosed above), And discloses, ‘wherein the low-pass filter is included in an envelope detector.’ (disclosed in Claim 2 and in Figure 4.2 in page-48). Regarding Claim 5, ‘The apparatus of claim 1’ (disclosed above), And discloses, ‘wherein the one or more processors are further configured to cause the UE to: derive the gap duration based at least in part on a device category of the UE.’ (Disclosure, a comparison table proposed second prototype was fabricated in an STMicroelectronics 90-nm CMOS technology. Comparison includes energy consumption of an IoT node with WuRx, JSSC’19 is [17], JSSC’20 is [35] and TMTT’22 is [36]. Includes parameters: technology, frequency, supply voltage, power nW, sensitivity, bit rate, codeword length [bit], error tolerance, FAR and temp range, page-75. Similar comparison table between the first prototype IoT node with WuRs and variants in page-63.) Regarding Claim 6, ‘The apparatus of claim 1’ (disclosed above), And discloses, ‘wherein the one or more processors are further configured to cause the UE to: derive the gap duration based at least in part on a modulation order of the wake-up signal.’(the modulation technique in the WuRx is OOK, page-2. And, the first prototype Gate oscillator WuRx includes OOK modulated, page-45 and second prototype, page-65.) Regarding Claim 7, ‘The apparatus of claim 1’ (disclosed above), And discloses, ‘wherein the one or more processors are further configured to cause the UE to: derive the gap duration based at least in part on a carrier frequency of the wake-up signal.’ (In Fig. 3.4 illustrates components includes the delay block, the edge detector and the gated oscillator. DDin generated by delay block is a delayed replica of Din, τd being the time delay. The maximum number of consecutive bits Nm adjusted by frequency calibration, the difference between rise and fall delay of the delay block (Section 3.2.3 Gated-oscillator based clock and data recover, page-36 [0008-0010, 0012], page-37 [0013], page-38 [0013, 0017]). The WuRx includes OOK-modulate and with a 433 MHz carrier frequency, page-65.) Regarding Claim 8, Similar to Claim 1 apparatus claim, ‘A method of wireless communication performed by a user equipment (UE), comprising: receiving a wake-up signal that includes at least a clock acquisition section, a data section, and a gap duration that is positioned between the clock acquisition section and the data section; and configuring, within the gap duration, receiver hardware using information that is based at least in part on the clock acquisition section.’ Regarding Claim 9, ‘The method of claim 8’ (disclosed above), Similar to Claim 2 disclosed above, ‘wherein configuring the receiver hardware comprises: configuring a cutoff frequency of a low-pass filter.’ Regarding Claim 10, ‘The method of claim 9’ (disclosed above), Similar to Claim 3 disclosed above, ‘wherein the information comprises at least one of: a symbol duration, or a chip length.’ Regarding Claim 11, ‘The method of claim 9’ (disclosed above), Similar to Claim 4 disclosed above, ‘wherein the low-pass filter is included in an envelope detector.’ Regarding Claim 12, ‘The method of claim 8’ (disclosed above), Similar to Claim 5 disclosed above, ‘further comprising: deriving the gap duration based at least in part on a device category of the UE.’ Regarding Claim 13, ‘The method of claim 6’ (disclosed above), Similar to Claim 6 disclosed above, ‘further comprising: deriving the gap duration based at least in part on a modulation order of the wake-up signal.’ Regarding Claim 14, ‘The method of claim 8’ (disclosed above), Similar to Claim 7 disclosed above, ‘further comprising: deriving the gap duration based at least in part on a carrier frequency of the wake-up signal.’ Regarding Claim 15, Similar to claim 1 non-transitory and CRM, ‘A non-transitory computer-readable medium storing a set of instructions for wireless communication, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a user equipment (UE), cause the UE to: receive a wake-up signal that includes at least a clock acquisition section, a data section, and a gap duration that is positioned between the clock acquisition section and the data section; and configure, within the gap duration, receiver hardware using information that is based at least in part on the clock acquisition section.’ Regarding Claim 16, ‘The non-transitory computer-readable medium of claim 15’ (disclosed above), Similar to Claim 2 disclosed above, ‘wherein the one or more instructions, that cause the UE to configure the receiver hardware, cause the UE to: configure a cutoff frequency of a low-pass filter.’ Regarding Claim 17, ‘The non-transitory computer-readable medium of claim 16’ (disclosed above), Similar to Claim 3 disclosed above, ‘wherein the information comprises at least one of: a symbol duration, or a chip length.’ Regarding Claim 18, ‘The non-transitory computer-readable medium of claim 15’ (disclosed above), Similar to Claim 4 disclosed above, ‘wherein the one or more instructions further cause the UE to: derive the gap duration based at least in part on a device category of the UE.’ Regarding Claim 19, ‘The non-transitory computer-readable medium of claim 15’ (disclosed above), Similar to Claim 6 disclosed above, ‘ wherein the one or more instructions further cause the UE to: derive the gap duration based at least in part on a modulation order of the wake-up signal.’ Regarding Claim 20, ‘The non-transitory computer-readable medium of claim 15’ (disclosed above), Similar to Claim 7 disclosed above, ‘wherein the one or more instructions further cause the UE to: derive the gap duration based at least in part on a carrier frequency of the wake-up signal.’ Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: D’Addato, M., et al. "Nanowatt clock and data recovery for ultra-low power wake-up receivers." Proceedings of the 2020 International Conference on Embedded Wireless Systems and Networks (EWSN 2020), Lyon, France. 2020. Presents baseband logic of a wake-up receivers (WuRx). And, the baseband logic includes a control logic with addressing capabilities and a clock and data recovery block based on a gated oscillator. It ensure phase alignment between the received data and the clock with high energy efficiency, section-5, Conclusion, page-229. D’Addato, Matteo, et al. "A gated oscillator clock and data recovery circuit for nanowatt wake-up and data receivers." Electronics 10.7 (2021): 780. (Year: 2021). Chen, Shih‐En, et al. "Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery." IET Circuits, Devices & Systems 14.2 (2020): 168-175. (Year: 2020) . This literature contain several approaches for improving the sensitivity of Wake-up Receiver (WuRx) devices. Ultra-low power WuRx). In Fig. 1 illustrates RF communication scheme with aux WuRx. Disclosure, WuRx architecture depicted in Fig. 2. The main components include an RF detector with an embedded impedance matching network, an IF amplifier, a baseband (BB) amplifier, a hysteresis comparator, clock and data recovery circuitry, and clock generation circuitry for input synchronized switching as well as double-sampling operation. In Fig. 1 WuRx and Fig. 12 illustrates Manchester coding bit stream. PNG media_image3.png 827 785 media_image3.png Greyscale Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Syed Ahmed whose telephone number is (703)-756-5308. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.A./Examiner, Art Unit 2466 /CHRISTOPHER M CRUTCHFIELD/Primary Examiner, Art Unit 2466