Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-14 are currently pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2024, 0620/2025 has been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Form PTO-1449 is signed and attached hereto.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “plural processing units” and “at least one accumulator unit” in claim 1. These nonce terms perform functional limitations. The “plural processing units” performs the functions of “receive at least one portion of input data and process at least one portion of an arithmetical/logical operation on the data” and “forward its processed data to a next processing unit and/or to the at least one accumulator unit”. The “at least one accumulator unit” performs the function of “receive at least two portions of processed data from the configurable compute unit and to output accumulated data.” Neither are modified by sufficient corresponding structure to avoid interpretation under 35 U.S.C. § 112(f). In particular, the “configurable compute unit” and “data stream processor” are not specific structures that would obviate the above interpretation because these terms would also be nonce terms and are only not invoking 35 U.S.C. § 112(f) themselves because they aren’t recited as performing a function themselves and additionally because the “data stream processor” is in the preamble of the claim which does not invoke 35 U.S.C. § 112(f). The “configurable compute unit” does, however, invoke 35 U.S.C. § 112(f) in claims 2-5 and 7. The “plural processing units” also perform additional functions on claim 6 and the “at least one accumulator unit” performs further functions in claims 8-9. Claims 2-11 depend from claim 1 and also recite the limitations above that invoke 35 U.S.C. § 112(f) in claim 1. Thus, claims 1-12 are interpreted under 35 U.S.C. § 112(f).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim limitation “plural processing units”, “at least one accumulator unit” and “configurable compute unit” in claims 1-12 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but the disclosure, as originally filed, does not provide support for sufficient corresponding structure for the “at least one accumulator unit”. Although, the disclosure (par. 0050-0057) reasonably discloses structure corresponding to the “plural processing units” and the “configurable compute unit” but is silent as to the corresponding structure of the “at least one accumulator unit”. Examiner further notes that for computer-implemented technologies, structural support may be derived from a “computer” + “algorithm”, see MPEP § 2181, however, Examiner finds no support in the specification for a specific definite structure nor a general-purpose processor/computer programmed to carry out an algorithm corresponding the functions performed by the limitation (“at least one accumulator unit”) which invokes 35 U.S.C. 112 (f),
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-12 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claims 1-12 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AlA the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above in 112(f) interpretation for the limitation “at least one accumulator unit” the disclosure does not provide adequate structure to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. See MPEP § 2181(II)(B) “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to "A computer program comprising a computer program code, when loaded into a computer and executed thereon" is neither of the process, machine, manufacture, or composition of matter. Software per se is not one of the statutory category. The claim can be amended to recite "A non-transitory storage medium [an article of manufacture] comprising a computer program code, said computer program code configured to” to overcome the software per se rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 10-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu et al. (U.S. Pub. No. 20230205729 A1).
As per claim 1, Gu teaches the invention as claimed including a data stream processor comprising:
a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process at least one portion of an arithmetical/logical operation on the data (pa. 0005 An exemplary electronic circuit includes a two-dimensional systolic array of reconfigurable processing elements that are configured to communicate bidirectionally with neighboring reconfigurable processing elements; par. 0013 The exemplary method additionally includes receiving input data by the two-dimensional systolic array configured into column-CPU mode and performing standard computations on the input data by the two-dimensional systolic array; par. 0068 one PE serving as arithmetic logic unit (ALU); par. 0067 where the logic in the 8b multiplier and 32b adder are reused to generate control signals by performing numerical/logical operations);
an input to the configurable compute unit configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit (par. 0076 in FIG. 8, the PEs may receive the inputs from bottom AOMEM banks (configured as input memory 810); par. 0090 As also shown in FIG. 15, process 1500 may include receiving input data by the two-dimensional systolic array configured into row-CPU mode); and
at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data (par. 0005 Accumulator modules are configured to communicate with at least one reconfigurable processing element and memory unit of a row or column of the two-dimensional systolic array; par. 0074 each AOMEM bank in every column may serve as output memory 620 to store accumulated results … and the accumulation 640 may be performed downward with results passing down in each column from ROW0 to ROW9);
wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to the at least one accumulator unit (par. 0074 Activation 630 may be performed from right to left, input data may go through every PE in each row from right to left, and the accumulation 640 may be performed downward with results passing down in each column from ROW0 to ROW9).
As per claim 2, Gu further teaches: wherein the configurable compute unit further comprises a configuration operable to provide at least one instruction for execution by at least one of the plural processing units (par. 0013 The exemplary method also includes receiving input data by the two-dimensional systolic array configured in row-CPU mode and performing standard computations on the input data by the two-dimensional systolic array; par. 0077 In the row-CPU mode dataflow 900 shown in FIG. 9, every row may be configured as a 5-stage pipelined core, with every row's AOMEM banks serving as data cache 910. Instructions may be passed through the pipeline 920 from left to right).
As per claim 3, Gu further teaches: wherein the configurable compute unit further comprises a configuration input operable to provide at least one instruction to link an output of a first one of the plural processing units to an input of a second one of the plural processing units (par. 0074 Activation 630 may be performed from right to left, input data may go through every PE in each row from right to left; par. 0077 In the row-CPU mode dataflow 900 shown in FIG. 9, every row may be configured as a 5-stage pipelined core, with every row's AOMEM banks serving as data cache 910. Instructions may be passed through the pipeline 920 from left to right).
As per claim 4, Gu further teaches: wherein the configurable compute unit further comprises a configuration input operable to provide at least one instruction to link an output of at least one of the plural processing units to the at least one accumulator (par. 0011 the two-dimensional systolic array of reconfigurable processing elements may be reconfigurable into four modes … A second of these modes may be a column-accelerator mode wherein data flows from memory elements on a right side of the rows leftward toward a leftmost column of the two-dimensional systolic array in an activation process and data accumulates downward toward memory elements on a bottom side of the columns in an accumulation process; par. 0074 the accumulation 640 may be performed downward with results passing down in each column from ROW0 to ROW9. Instruction caches may be gated during accelerator mode).
As per claim 6, Gu further teaches: wherein at least one of the plural processing units is operable to execute an instruction on at least one of a set of data elements (par. 0013 method of performing deep neural network processing and computing processing may be executed in a two-dimensional systolic array of reconfigurable processing elements; par. 0077 In the row-CPU mode dataflow 900 shown in FIG. 9, every row may be configured as a 5-stage pipelined core, with every row's AOMEM banks serving as data cache 910. Instructions may be passed through the pipeline 920 from left to right).
As per claim 10, Gu further teaches: wherein at least two of the configurable compute units are configured to operate in a chain; and wherein processed data is passed directly between the configurable compute units (par. 0074 Activation 630 may be performed from right to left, input data may go through every PE in each row from right to left; Fig. 6).
As per claim 11, Gu further teaches: wherein at least four of the configurable compute units are configured to operate in a two-dimensional cluster; and wherein processed data is passed directly between the configurable compute units (par. par. 0011 the two-dimensional systolic array of reconfigurable processing elements may be reconfigurable into four modes … A second of these modes may be a column-accelerator mode wherein data flows from memory elements on a right side of the rows leftward toward a leftmost column of the two-dimensional systolic array in an activation process and data accumulates downward toward memory elements on a bottom side of the columns in an accumulation process; par. 0074 Activation 630 may be performed from right to left; input data may go through every PE in each row from right to left; Fig. 6).
As per claim 12, Gu teaches the invention as claimed including a method of operating a configurable compute unit of a data stream processor, the compute unit having plural processing units (pa. 0005 An exemplary electronic circuit includes a two-dimensional systolic array of reconfigurable processing elements), comprising:
receiving input data at one of the plural processing units in the configurable compute unit (par. 0013 The exemplary method additionally includes receiving input data by the two-dimensional systolic array configured into column-CPU mode and performing standard computations on the input data by the two-dimensional systolic array; par. 0068 one PE serving as arithmetic logic unit (ALU); par. 0067 where the logic in the 8b multiplier and 32b adder are reused to generate control signals by performing numerical/logical operations);
processing at least one portion of a repetitive arithmetical/logical operation on the data (par. 0013 The exemplary method additionally includes … performing standard computations on the input data by the two-dimensional systolic array; par. 0068 one PE serving as arithmetic logic unit (ALU); par. 0067 where the logic in the 8b multiplier and 32b adder are reused to generate control signals by performing numerical/logical operations); and
forwarding a result of the processing of at least one portion of a repetitive arithmetical/logical operation to a next processing unit and/or to the at least one accumulator unit par 0005 Accumulator modules are configured to communicate with at least one reconfigurable processing element and memory unit of a row or column of the two-dimensional systolic array; par. 0074 each AOMEM bank in every column may serve as output memory 620 to store accumulated results … and the accumulation 640 may be performed downward with results passing down in each column from ROW0 to ROW9).
A per claim 14, it is a computer program comprising computer program code having similar limitations as claim 12. Thus, claim 14 Is rejected for the same rationale as applied to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Meixner et al. (U.S. Pub. No. 20190327437 A1).
As per claim 5, Gu does not expressly describe: wherein the configurable compute unit is operable to cause at least one of the plural processing units to execute a visual processing primitive operation.
However, Meixner teaches: wherein the configurable compute unit is operable to cause at least one of the plural processing units to execute a visual processing primitive operation (par. 0096 Fig. 7 describes an architecture 700 for an image processor implemented in hardware and includes a plurality of stencil processor units 702_1 through 702_N; par. 00139-0190 describes a plurality of fundamental primitive operations implemented/performed by the image processor, including: a. Row/Column Sum Operation, b. Row/Column Prefix Sum Operation; c. Row/Column Find Min Operation, d. Matrix Multiply […] particularly useful for discrete fourier or cosine transforms (which are common primitives in compression and filtering) and to express larger matrix/multiply operations; e. Two-Dimensional Discrete Fourier Transform (2D DFT), f. FFT Butterfly and g. Block Match; par. 0199 the image processor architectural features described above may be applied to technical applications such as video processing, vision processing, image recognition and/or machine learning).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of using an image processor comprising a plurality of stencil processors to execute image/vision processing primitive operations of Meixner with the system and method of Gu resulting in a system and method which utilizes an image processor comprising a plurality of stencil processors for executing image/vision processing primitive operations. One of ordinary skill in the art would have been motivated to make this combination for the purpose performing operations such as statistics computation, noise suppression, and large scale down-sampling, accelerating box filters, computation of addresses for compaction operations, block matching post-processing, compression and filtering. noise reduction and accelerating convolutions (par. 0140, 0146, 0157, 0178). Furthermore, the ability to perform such image/vision processing primitive operations would have provided for simplifying how machines/computers understand images, and thereby allow for faster processing and higher adaptability.
As per claim 7, Meixner further teaches: wherein the configurable compute unit comprises a stencil operation processor (par. 0104 sheets of image data are loaded into a two-dimensional register array structure within the stencil processor 702; Fig. 9a, Stencil Processor 900, par. 0112).
As per claim 13, it is a method having similar limitations as claim 5. Thus, claim 13 is rejected for the same rationale as applied to claim 5.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Dally et al. (U.S. Pub. No. 20180046916 A1).
As per claim 8, Gu does not expressly describe: wherein the at least one accumulator unit is further operable to execute post-processing operations on at least one portion of processed data from the configurable compute unit.
However, Dally teaches: wherein the at least one accumulator unit is further operable to execute post-processing operations on at least one portion of processed data from the configurable compute unit (par. 0089 The PE 210 may begin processing of the next tile using the “primary” of accumulator array 340 while the post-processing unit 345 begins post-processing of the last tile in parallel using the “secondary” accumulator array 340).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the technique of performing post processing operations of Dally with the system and method of Gu resulting in a system and method which provides for executing post-processing operations on processed data as in Dally. One of ordinary skill in the art would have been motivated to make this combination for the purpose of achieving performance improvements while still being energy-efficient (par. 0143).
As per claim 9, Gu teaches: Gally further teaches: at least one accumulator unit (par. 0005 Accumulator modules are configured to communicate with at least one reconfigurable processing element). Dally further teaches: operable to execute a data reduction operation on the at least one portion of processed data from the configurable compute unit (par. 0072 while registers in the accumulator array 340 storing partial products for the previous tile are accessed to resolve halos and encode the resulting output activations into the compressed format [data reduction]; par. 0076 post-processing unit 345 performs the following tasks: … (3) compress the output activations into the compressed-sparse form [performs data reduction] and write the compressed-sparse output activations into the output activations buffer 350 and write the output positions associated with the compressed-sparse output activations into the indices buffer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent No. 6000835 A teaches Method And System For Performing An L.sub.11 Norm Operation.
U.S. Pub. No. 20240303218 A1 teaches a reconfigurable processor for adaptively configuring a pipeline depth and performing multi-stage pipeline control over a reconfigurable array.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Willy W. Huaracha whose telephone number is (571)270-5510. The examiner can normally be reached on M-F 8:30-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached on (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WH/
Examiner, Art Unit 2195
/BRADLEY A TEETS/ Supervisory Patent Examiner, Art Unit 2197
Prosecution Insights