Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant office action having application number 18/782768, filed on July 24, 2024, has claims 1-15 pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/20/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 recites a method for co-designing transformer-accelerator pairs that includes: using a transformer embedding to generate a computational graph and transformer model; running the graph through a surrogate model and outputting accuracy data; using an accelerator embedding and transformer model to simulate training/inference and output hardware-performance data; sending the hardware-performance and model-accuracy data to a co-design optimizer; and generating a transformer-accelerator or transformer-edge-device pair. The published application describes these limitations substantially in these terms.
Step 1 — Statutory category. Claim 1 is nominally directed to a “method” and therefore falls within the statutory process category. The analysis therefore proceeds to Step 2A. See MPEP §2106.03.
Step 2A, Prong One — Claim recites an abstract idea. The limitations of claim 1 recite mathematical concepts. In particular:
a “transformer embedding” and an “accelerator embedding” are numerical or mathematical representations of model and hardware characteristics;
generating and processing a computational graph represents model operations mathematically;
a surrogate model mathematically predicts model accuracy;
simulation of training and inference calculates predicted hardware-performance characteristics;
the co-design optimizer evaluates accuracy and hardware-performance data to identify an optimized model/hardware combination.
Thus, the claim recites mathematical relationships, mathematical calculations, and mathematical optimization. Mathematical concepts constitute a recognized grouping of abstract ideas under the USPTO eligibility framework. MPEP §2106.04(a)(2).
The abstract idea can therefore be characterized as:
mathematically modeling and optimizing a transformer architecture and corresponding hardware architecture based on predicted accuracy and hardware-performance information.
This characterization does not improperly generalize the claim because it tracks the actual claimed operations: embeddings, graph generation, surrogate prediction, simulation, numerical performance information, and optimization.
Step 2A, Prong Two — The judicial exception is not integrated into a practical application. The additional elements beyond the mathematical concepts include a “transformer model,” an “accelerator” or “edge device,” and use of simulated training/inference tasks. These limitations do not impose a meaningful technological limitation on the abstract optimization.
The claim does not require manufacturing or fabricating an accelerator, physically modifying accelerator circuitry, configuring the selected accelerator with the resulting transformer model, or actually deploying the selected pair to perform a real-world task. Rather, the recited accelerator and transformer supply the technological environment whose characteristics are represented, simulated, and optimized.
The final limitation requires merely generating an output transformer-accelerator or transformer-edge-device pair. The output remains the result of the mathematical optimization rather than requiring a subsequent technological act performed using the resulting pair.
Similarly, simulating training and inference does not itself integrate the exception into a practical application because the simulation is used to derive the numerical hardware-performance data that are supplied to the optimizer. The simulation therefore constitutes part of the mathematical evaluation itself.
The claim therefore does not improve the functioning of a computer or other technology through a specifically claimed technological implementation; rather, it uses computer technology as the environment for carrying out the mathematical modeling and optimization. Merely implementing an abstract idea using a computer, without more, does not integrate the exception into a practical application. MPEP §2106.05(f).
Accordingly, claim 1 is directed to the judicial exception under Step 2A.
Step 2B — No significantly more. The additional limitations, considered individually and as an ordered combination, do not amount to significantly more than the abstract idea.
The transformer model, computational graph, surrogate model, accelerator representation, simulator, and optimizer perform their ordinary computational functions: representing information, processing a model, predicting output, simulating performance, and optimizing numerical parameters. Claim 1 does not recite any particular unconventional accelerator architecture, particular improvement to a processor or memory subsystem, specialized simulation technique, new computational-graph structure, or specific technical implementation of the optimizer.
Instead, these additional elements merely provide generic computational implementation of the mathematical optimization. The ordered combination likewise amounts to obtaining numerical representations, predicting characteristics, evaluating those characteristics, and selecting an optimized result.
Accordingly, claim 1 does not recite an inventive concept sufficient to transform the abstract idea into patent-eligible subject matter and is rejected under 35 U.S.C. §101.
Claim 7
Claim 7 recites a system for co-designing transformer-accelerator pairs comprising one or more processing units configured collectively to perform substantially the same operations recited in claim 1. The application’s description confirms that claim 7 performs graph/model generation, surrogate-model accuracy evaluation, accelerator/model simulation, co-design optimization, and output of a transformer/hardware pair.
Step 1. Claim 7 is nominally directed to a machine/system and therefore falls within a statutory category.
Step 2A, Prong One. The processing units are configured to perform the same mathematical modeling and optimization identified for claim 1. Specifically, the claim represents architectures through embeddings, processes a computational graph, predicts accuracy, simulates hardware performance, processes the resulting numerical information with an optimizer, and outputs an optimized transformer/hardware pair.
Thus, the claimed processing units are configured to perform the abstract idea of:
mathematically evaluating and optimizing transformer and accelerator architectures based on predicted accuracy and hardware-performance characteristics.
The change in statutory form from method to system does not alter the underlying abstract nature of these operations.
Step 2A, Prong Two. The additional element is principally “one or more processing units.” The processing units merely execute the mathematical modeling, simulation, and optimization. No specialized processor architecture is required, and the claim does not recite a structural modification to those processors.
The claim also does not require the processing units to fabricate, install, configure, or physically operate the optimized accelerator/model pair. Instead, they generate the optimized pair as output.
Accordingly, the processing units amount to a computer implementation of the mathematical concepts rather than integration of those concepts into a practical application.
Step 2B. The recited processing units perform generic computer functions—executing instructions, generating model representations, running prediction/simulation, processing numerical data, and generating output. Nothing in claim 7 requires the processing units themselves to operate in an unconventional manner.
Considering the claim as a whole, reciting generic processors configured to execute the abstract operations does not add an inventive concept. See MPEP §2106.05(f), explaining that merely applying an abstract idea with a generic computer is insufficient.
Claim 7 is therefore rejected under §101.
Claim 9
Claim 9 recites a non-transitory computer-readable storage medium having stored thereon a computer program for execution by one or more processing units, where the processing units collectively perform essentially the claim-1 co-design method. The application expressly describes claim 9 in these terms.
Step 1. A non-transitory computer-readable storage medium is nominally a statutory manufacture.
Step 2A, Prong One. The stored instructions cause the processor to perform the same abstract mathematical operations identified for claim 1: generating a computational graph from an embedding, obtaining predicted accuracy, simulating hardware performance, sending numerical performance/accuracy data to an optimizer, and generating a selected model/hardware pair.
The underlying judicial exception therefore remains:
mathematical representation, prediction, simulation, and optimization of a transformer architecture and hardware architecture.
Encoding the abstract process as computer-readable instructions does not alter the character of the claimed operations.
Step 2A, Prong Two. The storage medium and processing units merely provide the computer implementation through which the abstract mathematical method is performed. The medium does not impose any meaningful technological constraint on the underlying optimization, nor does the claim recite a new type of storage technology, processor architecture, or improvement in computer-storage operation.
The medium therefore serves merely as a vehicle for instructions implementing the judicial exception.
Step 2B. The recitation of a non-transitory computer-readable medium and generic processing units amounts to conventional computer implementation of the abstract process. The claim does not require any unconventional storage structure, programming arrangement, processor operation, or hardware interaction beyond execution of the claimed mathematical optimization.
The claim as a whole therefore does not amount to significantly more than the judicial exception.
Claim 9 is accordingly rejected under §101.
Claim 11
Claim 11 recites a method for profiling processing-unit performance comprising: converting a surrogate model to a computational graph; training a machine-learning model on the computational graph; running inference for a natural-language-processing task on at least one processing unit; and outputting hardware-performance data generated from the NLP task. The application describes this embodiment at lines corresponding to these same operations.
Step 1. Claim 11 recites a method and therefore falls within the statutory process category.
Step 2A, Prong One. Claim 11 recites mathematical concepts.
Converting a surrogate model to a computational graph represents mathematical/model relationships in graph form. Training a machine-learning model involves mathematical adjustment of model parameters to minimize or optimize an objective. Running inference performs mathematical operations on input data using the trained model. Profiling resulting hardware-performance data comprises collecting and calculating numerical measures associated with those operations.
The claimed abstract idea can therefore be characterized as:
mathematically modeling and evaluating execution of a machine-learning model to determine processor-performance characteristics.
The use of an NLP task does not remove these mathematical operations from the abstract-idea grouping. It merely defines the type of data/model task to which the mathematical operations are applied.
Step 2A, Prong Two. The additional elements include “at least one processing unit” and performing an NLP inference task.
These limitations do not integrate the exception into a practical application. The processing unit merely executes the mathematical model so that performance information can be obtained. The claimed output is hardware-performance data; the claim does not require that the processing unit thereafter be reconfigured or improved based on the profile.
Likewise, the NLP task serves as the environment in which the profiling is performed. Claim 11 does not require a specific technical improvement to natural-language processing itself.
The claim therefore uses computer execution as a mechanism for collecting the numerical data that constitute the object of the profiling operation.
Step 2B. The processing unit performs its ordinary function of executing machine-learning inference. The computational graph and trained machine-learning model likewise perform ordinary mathematical-model functions. The claim recites no particular processor architecture, memory arrangement, scheduling technique, compilation technique, or hardware modification that would constitute an inventive technological implementation.
Considered as an ordered combination, the claim converts a model representation, trains the model, executes it, and reports performance information. These are the very operations underlying the abstract performance-evaluation concept rather than additional elements supplying an inventive concept.
Claim 11 is therefore rejected under §101.
Claim 14
Claim 14 recites a method for profiling accuracy of a transformer model comprising: converting a set of transformer-model architecture parameters to a computational graph; generating a transformer model from the computational graph; passing the transformer model through a model-training module; and outputting accuracy data of the trained transformer model. The publication expressly describes those operations.
Step 1. Claim 14 is a method and therefore falls within the statutory process category.
Step 2A, Prong One. Claim 14 recites mathematical concepts.
The “set of transformer model architecture parameters” comprises numerical/model parameters defining the architecture. Converting those parameters into a computational graph constitutes mathematical representation of the architecture. Generating the transformer model from the graph and training that model involve mathematical operations upon model parameters and weights. Calculating and outputting model accuracy similarly involves mathematical evaluation of model performance.
The abstract idea can therefore be characterized as:
mathematically constructing, training, and evaluating a transformer model based on architecture parameters.
This falls within the mathematical-concepts grouping of abstract ideas.
Step 2A, Prong Two. The additional elements include the transformer model and the model-training module. These limitations do not integrate the mathematical concepts into a practical application.
The model-training module is invoked only to perform the mathematical training operation, while the transformer model is the mathematical model being evaluated. The endpoint of the claim is merely accuracy data. There is no requirement that the trained transformer thereafter control a machine, improve a physical device, be deployed to a specific technological environment, or cause a particular real-world technological result.
The claim therefore remains focused on creating and evaluating a mathematical model rather than applying that model in a specifically claimed practical technological process.
Step 2B. The additional elements merely implement the abstract model-training/evaluation concept using ordinary computing functions. The claim does not specify a new training algorithm, new transformer architecture, unconventional computational graph, specialized hardware, or particular technical mechanism for improving processor operation.
The ordered combination—architecture parameters → graph → transformer model → training → accuracy output—still amounts to mathematical construction and evaluation of a machine-learning model.
Consequently, the claim does not contain an inventive concept that amounts to significantly more than the judicial exception.
Claim 14 is therefore rejected under §101.
Dependent claims 2-6, 8, 10, 12-13 and 15 are rejected under the same reasoning as their independent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 USC 102(a)(1) as being anticipated by Zehngut et al. (US 20220147680 A1) (hereinafter Zehngut).
As per claims 1, 7, 9, 11 and 14 Zehngut discloses using a transformer embedding to generate a computational graph and a transformer model [NAS component 135 selects a value of a coarse dimension during a NAS using a controller based search algorithm, where the controller based search algorithm includes a policy function for selecting the value of the coarse dimension. In some examples, NAS component 135 identifies a fine dimension for the NAS based on the value of the coarse dimension, paragraphs 29-30 and 35]; running the computational graph through a surrogate model and outputting accuracy data of said surrogate model [NAS methods may operate in an intractable search space that is spanned by a set of dimensions formed by such neural network architecture attributes. NAS methods may provide for automatic design of neural network architectures such that both performance of a task (e.g., neural network output accuracy) and the expected efficiency (e.g., the resulting power, performance, and area (PPA) parameters) are optimized, paragraph 49]; using an accelerator embedding and said transformer model to simulate training and inference tasks and outputting hardware performance data of said transformer model [efficiency of a neural network and hardware architecture are measured based on a combination of consumed power, performance and latency metrics, hardware area,, paragraph 18, also see paragraphs 32, 40-41]; sending the hardware performance data and model accuracy data to a co-design optimizer [NAS methods may provide for automatic design of neural network architectures such that both performance of a task (e.g., neural network output accuracy) and the expected efficiency (e.g., the resulting power, performance, and area (PPA) parameters) are optimized. In some cases, NAS methods may implement controller based learning techniques such as reinforcement learning or evolutionary learning. In other examples, NAS methods are based on differential algorithm-based techniques, paragraph 49]; and generating an output transformer-accelerator or a transformer-edge-device pair from said co-design optimizer [variable HW prediction component 150 predicts PPA parameters using a variable hardware predictor. In some examples, variable HW prediction component 150 iteratively updates the neural architecture parameters and the hardware parameters based on the predicted PPA parameters. In some examples, variable HW prediction component 150 generates a hardware design based on the updated hardware parameters, paragraph 32].
As per claim 2, Zehngut discloses, wherein the transformer model and accelerator embedding are the output transformer-accelerator or a transformer-edge-device pair [updating the neural-architecture parameters and hardware parameters and generating a hardware design, paragraph 32].
As per claim 3, Zehngut discloses wherein the hardware performance data includes: latency, energy leakage, dynamic energy, and chip area [power. Performance, latency and hardware area as PPA measures, paragraphs 18 and 40].
As per claim 4, Zehngut discloses wherein the latency, energy leakage, dynamic energy, chip area, and model accuracy are optimizable performance parameters [optimizing neural-network output accuracy together with PPA, paragraph 49, and identify latency and area within PPA paragraphs 18 and 40].
As per claim 5, Zehngut discloses wherein the dynamic energy and energy leakage parameters are optimized where a device’s power envelope is highly restricted [Neural Architecture Search (NAS) techniques may be implemented for automatic design of neural network architectures such that both performance of a task (e.g. neural network accuracy) and the expected efficiency (e.g., the resulting power, performance, and area (PPA) parameters) are optimized, paragraph 18].
As per claim 6, Zehngut discloses wherein the model accuracy is optimized for server-side deployments [NAS methods may operate in an intractable search space that is spanned by a set of dimensions formed by such neural network architecture attributes. NAS methods may provide for automatic design of neural network architectures such that both performance of a task (e.g., neural network output accuracy) and the expected efficiency, paragraph 49].
As per claim 8, 10 and 12, Zehngut discloses wherein the hardware performance data includes: latency, energy leakage, dynamic energy, and chip area [Hardware devices, such as an ASIC, are designed to execute applications while optimizing efficiency. Efficiency may be measured as a combination of consumed power, performance/latency, and the resulting area (e.g., which may be referred to as PPA parameters), paragraph 40].
As per claim 13, Zehngut discloses wherein the at least one processing unit is one of a graphics processing unit and a central processing unit [A processor 125 is an intelligent hardware device, (e.g., a general-purpose processing component, a digital signal processor (DSP), a CPU, paragraph 25].
As per claim 15, Zehngut discloses wherein the model training module is tuned during transformer model training [Training the system may involve supplying values for the inputs, and modifying edge weights and activation functions (algorithmically or randomly) until the result closely approximates a set of desired outputs, paragraph 34].
Conclusion
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September 30, 2026
/NOOSHA ARJOMANDI/Primary Examiner, Art Unit 2166
