Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 2, 6, and 8-20 were withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 11, 2026.
Upon further review, the examiner noted that the species restriction, filed on January 23, 2026, was improper, but the sub-species restriction, filed in the same office action, was proper. Therefore, the species restriction has been withdrawn, and the sub-species restriction stands.
A telephone conversation was initiated by the examiner with the attorney of record, Sangki Park, Reg. No. 77,261, on May 28, 2026, to explain the further review of the restriction. Affirmation of this election was made by applicant, that the claims directed toward elected sub-species A would be examined. Claims 2, 6-8, 12-14, and 20 were withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 24, 2024 & December 2, 2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 5, 16, and 17 are objected to because of the following informalities:
Claim 5 (line 3) recites "wherein the first terminal of the third transistor is a drain, the second terminal is a source". From claim 1, the third transistor appears to be MP2, wherein the first terminal (MP2-source) is connected to the power source (VDD). Therefore, this claim appears to recite the drain and source with the opposite transistor terminal. It appears that the claim language from claim 4 was copied into claim 5, and the examiner will interpret the claim by the claim language of the third transistor shown in claim 1.
Claim 16 (line 3) recites "configured to generate mirror current of". It appears the claim language should state "a mirror current" as shown in claim 1.
Claim 17 (line 5) recites "where a first temperature is lower a reference temperature". It appears the claim language is missing word(s).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 9-11, and 15-16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wong et al. (US 6724176 B1); hereinafter Wong.
Regarding Claim 1, Wong discloses a current generator, comprising [Fig. 3]: an amplifier [310] configured to receive a reference voltage through a first input terminal [voltage input into inverting terminal of 310], receive a feedback voltage through a second input terminal [voltage input into non-inverting terminal of 310], and generate an output voltage [output of 310] based on a difference of the reference voltage and the feedback voltage [inherent to operation of operational amplifier]; a first resistor [331] having a first end [upper end of 331 directly connected to non-inverting terminal of 310] connected to the second input terminal and a second end connected to ground [lower end of 331 directly connected to ground]; a second resistor [332] having a first end [upper end of 332] connected to a first node [node at upper end of 332] connected to the second input terminal; a first transistor [320] having a first terminal [320-emitter] connected to the second resistor and a second terminal [320-collector] and a control terminal [320-base] connected to ground; a second transistor [301] having a gate [301-gate] connected to an output terminal of the amplifier [310-output], a first terminal [301-drain; column 6, lines30-31] connected to the first node, a second terminal [301-source; column 6, lines 22-25] connected to a power source [VDD], and configured to transfer a first current [I5] through the first terminal; and a third transistor [304] having a gate [304-gate] connected to the output terminal of the amplifier, a first terminal [304-source; column 6, lines 22-25] connected to the power source, and configured to transfer a second current [I8] that is a mirror current of the first current [column 6, lines 24-29] through the second terminal.
Regarding Claim 3, Wong discloses the current generator of claim 1, wherein the first transistor is a Positive-Negative-Positive (PNP)-type bipolar junction transistor (BJT) [column 5, lines 44-45], and wherein the first terminal of the first transistor is an emitter [inherent in Fig. 3], the second terminal is a collector [inherent in Fig. 3], and the control terminal is a base [inherent in Fig. 3; column 3, lines 36-44].
Regarding Claim 4, Wong discloses the current generator of claim 1, wherein the second transistor is a P-channel metal-oxide semiconductor field-effect transistor (MOSFET) [column 5, line 34], and wherein the first terminal of the second transistor is a drain [301-drain; column 6, lines30-31], the second terminal is a source [301-source; column 6, lines 22-25], and the control terminal is a gate [301-gate; column 6, lines 21-22].
Regarding Claim 5, as best understood, Wong discloses the current generator of claim 1, wherein the third transistor is a P-channel MOSFET [column 5, line 34], and wherein the first terminal of the third transistor is a drain [per claim objection interpretation: 304-source is the first terminal; column 6, lines 22-25], the second terminal is a source [per claim objection interpretation: 304-drain is the second terminal], and the control terminal is a gate [304-gate; column 6, lines 21-22].
Regarding Claim 9, Wong discloses [Fig. 2/Fig. 3/Fig. 4] a semiconductor device [200], comprising: a controller [225] configured to generate a voltage control signal [output of 225]; a voltage generator [210] configured to generate a reference voltage [output of 210] based on the voltage control signal [output of 210 based on output of 240 based on output of 225; column 5, lines 7-17]; and a current generator [240/400] configured to generate a first current [IR331] having a constant magnitude in a first region where a first temperature [negative temperature coefficient] is lower than a reference temperature [see Fig. 5D below], and generate a second current [IR332] whose magnitude is proportional to a second temperature [positive temperature coefficient] in a second region where the second temperature is greater than or equal to the reference temperature, wherein the reference temperature is based on the reference voltage.
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Regarding Claim 10, Wong discloses the semiconductor device of claim 9,
wherein the current generator comprises a bipolar junction transistor (BJT) [320], and
wherein the reference temperature comprises a temperature of the BJT when an emitter-base voltage intersects the reference voltage [Abstract].
Regarding Claim 11, Wong discloses the semiconductor device of claim 10, wherein the current generator is configured to generate the second current based on a difference between the reference voltage and the emitter-base voltage [Abstract].
Regarding Claim 15, Wong discloses the semiconductor device of claim 9, wherein the current generator comprises: an amplifier [310] configured to receive the reference voltage through a first input terminal [voltage input into inverting terminal of 310] and receive a feedback voltage of the reference voltage through a second input terminal [voltage input into non-inverting terminal of 310]; and a first transistor [301] having a gate [301-gate] connected to an output terminal of the amplifier [310-output], the first transistor configured to flow the first current in the first region and flow the second current in the second region.
Regarding Claim 16, Wong discloses the semiconductor device of claim 15, wherein the current generator further comprises a second transistor [304] having a gate [304-gate] connected to the output terminal of the amplifier, the second transistor configured to generate mirror current of the first current and the second current [column 6, lines 24-29].
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by MacLean (US 6954059 B1); hereinafter MacLean.
Regarding Claim 1, MacLean discloses a current generator, comprising [Fig. 1]: an amplifier [A1] configured to receive a reference voltage through a first input terminal [voltage input into inverting terminal of A1], receive a feedback voltage through a second input terminal [voltage input into non-inverting terminal of A1], and generate an output voltage [output of A1] based on a difference of the reference voltage and the feedback voltage [inherent to operation of operational amplifier]; a first resistor [Rb1] having a first end [upper end of Rb1 directly connected to node V1] connected to the second input terminal and a second end connected to ground [lower end of Rb1 directly connected to ground]; a second resistor [Rp] having a first end [upper end of Rp] connected to a first node [node V1] connected to the second input terminal; a first transistor [Q1] having a first terminal [Q1-emitter] connected to the second resistor and a second terminal [Q1-collector] and a control terminal [Q1-base] connected to ground; a second transistor [M1] having a gate [M1-gate] connected to an output terminal of the amplifier [A1-output], a first terminal [M1-drain] connected to the first node, a second terminal [M1-source] connected to a power source [Vdd], and configured to transfer a first current [I1] through the first terminal; and a third transistor [M3] having a gate [M3-gate] connected to the output terminal of the amplifier, a first terminal [M3-source] connected to the power source, and configured to transfer a second current [I3] that is a mirror current of the first current [column 4, line 40] through the second terminal.
Regarding Claim 3, MacLean discloses the current generator of claim 1, wherein the first transistor is a Positive-Negative-Positive (PNP)-type bipolar junction transistor (BJT) [column 3, lines 29-30], and wherein the first terminal of the first transistor is an emitter [inherent in Fig. 1], the second terminal is a collector [inherent in Fig. 1], and the control terminal is a base [inherent in Fig. 1; column 3, lines 29-33].
Regarding Claim 4, MacLean discloses the current generator of claim 1, wherein the second transistor is a P-channel metal-oxide semiconductor field-effect transistor (MOSFET) [column 3, lines 52-53], and wherein the first terminal of the second transistor is a drain [M1-drain; column 3, lines 55-56], the second terminal is a source [M1-source; column 3, lines 52-55], and the control terminal is a gate [M1-gate; column 3, lines 53-55].
Regarding Claim 5, as best understood, MacLean discloses the current generator of claim 1, wherein the third transistor is a P-channel MOSFET [column 3, lines 52-54], and wherein the first terminal of the third transistor is a drain [per claim objection interpretation: M3-source is the first terminal; column 3, lines 52-55], the second terminal is a source [per claim objection interpretation: M3-drain is the second terminal; column 3, lines 55-56], and the control terminal is a gate [M3-gate; column 3, lines 54-55].
Claims 9-11 and 15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lai et al. (US 11393512 B2); hereinafter Lai.
Regarding Claim 9, Lai discloses a semiconductor device [Fig. 2B/3/4], comprising: a controller [200] configured to generate a voltage control signal [Vo], [column 4, line 61 - column 5, line 2]; a voltage generator [404] configured to generate a reference voltage [Vbe of transistor 11] based on the voltage control signal; and a current generator [402] configured to generate a first current [PTAT current, from PTAT current source 406/500] having a constant magnitude in a first region where a first temperature [column 5, lines 3-17] is lower than a reference temperature [column 5, lines 3-17], and generate a second current [ZTC current, from ZTC current source 408] whose magnitude is proportional to a second temperature in a second region [column 5, lines 3-17] where the second temperature is greater than or equal to the reference temperature [column 7, lines 16-43], wherein the reference temperature is based on the reference voltage [column 7, lines 8-10].
Regarding Claim 10, Lai discloses the semiconductor device of claim 9, wherein the current generator comprises a bipolar junction transistor (BJT) [Q1/Q2], and wherein the reference temperature comprises a temperature of the BJT when an emitter-base voltage intersects the reference voltage [column 9, lines 29-52].
Regarding Claim 11, Lai discloses the semiconductor device of claim 10, wherein the current generator is configured to generate the second current based on a difference between the reference voltage and the emitter-base voltage [column 9, lines 29-52].
Regarding Claim 15, Lai discloses the semiconductor device of claim 9, wherein the current generator comprises: an amplifier [416] configured to receive the reference voltage through a first input terminal [420] and receive a feedback voltage of the reference voltage through a second input terminal [422]; and a first transistor [426] having a gate [426-gate] connected to an output terminal of the amplifier [424], the first transistor configured to flow the first current in the first region and flow the second current in the second region.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wong, in view of Aziz et al. (US 20140169426 A1); hereinafter Wong, in view of Aziz.
Regarding Claim 17, Wong discloses a current generator [240/400] configured to generate a bias current [I5] having a constant magnitude in a first region where a first temperature [negative temperature coefficient] is lower than a reference temperature [see Fig. 5D under claim 9], generate the bias current whose magnitude is proportional to the first temperature in a second region [positive temperature coefficient], where the first temperature is greater than or equal to the reference temperature [see Fig. 5D under claim 9], and transfer the bias current to the amplifier [thru the feedback path]. Wong does not explicitly disclose wherein an equalizer configured to perform equalization to data received through a communication channel by using an amplifier.
However, Aziz discloses a receiver [130], comprising: an equalizer [134] configured to perform equalization to data [paragraph 0032] received through a communication channel [backplane channel 120] by using an amplifier [132]; and a current generator [Fig. 3; current are generated from 340/342 as output currents thru 344]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Aziz in the invention of Wong, with the expected benefit of improving linearity and reducing distortion. This method of improving Wong using Aziz was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Aziz. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wong and Aziz to obtain the invention: incorporating the equalizer and current generator together.
Regarding Claim 18, Wong, in view of Aziz, discloses the receiver of claim 17, wherein the current generator comprises a bipolar junction transistor (BJT) [Wong; 320], and wherein the current generator is configured to generate the bias current based on temperature characteristics of the bipolar junction transistor [Wong; Abstract].
Regarding Claim 19, Wong, in view of Aziz, discloses the receiver of claim 17, wherein the equalizer comprises a continuous-time linear equalizer (CTLE) [Aziz; paragraph 0004], and wherein the current generator is configured to transfer the bias current to the continuous-time linear equalizer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gong et al. (CN 112034922 A) & Li et al. (US 20230246885 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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