Prosecution Insights
Last updated: October 01, 2026
Application No. 18/783,057

MEMORY DEVICE USING ERROR CHECK AND SCRUB WITH SHARED SCRUB LOOP

Non-Final OA §103
Filed
Jul 24, 2024
Priority
Jun 12, 2024 — provisional 63/658,967
Examiner
CHASE, SHELLY A
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
3 (Non-Final)
95%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
728 granted / 768 resolved
+39.8% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
8 currently pending
Career history
787
Total Applications
across all art units

Statute-Specific Performance

§101
13.1%
-26.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
13.3%
-26.7% vs TC avg
§112
14.9%
-25.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 768 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 to 20 are presented for examination. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8-19-2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 to 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (USPAP 2011/0289386). Claim 1: Yang substantially teaches the claimed invention. Yang teaches a method and an apparatus for eliminating data errors on a spin moment transfer (SMT) magnetic random-access memory (MRAM) cells, the apparatus comprising: a scrub machine (“controller”) that is used to scrub disturb errors from an SMT MRAM device (see figs 2 to 4 and par. 0046). Yang teaches that the scrub machine receives an externally provided address (2560 and externally provided data (258) (“source”) and based on a read or write operation the externally provided data is transferred to the memory array (205) (see par. 0035). Yang teaches that during a write operation, the externally provided data is transferred by the memory data bus to an ECC encoder wherein the ECC encoder generates the necessary error correction data bits (see par. 0035). Yang teaches that during a read operation, an array address input is transferred to the memory location to access a selected grouping of memory cells (see par. 0036). Yang teaches that the scrub machine determines if the corrected data has exceeds the scrub threshold and transfer the corrected data to the ECC encoder where it is re-encoded and stored within the selected location within the memory array (see par. 0036). Yang teaches that for a specific address, retrieve the data and its corresponding ECC code from the SMT MRAM device and transfer the data and its ECC to an ECC decoder to check for errors (see par. 0047). Yang teaches that the data and its corresponding ECC are scrubbed by the scrub machine when errors are detected to in the corrected data (see par. 0049). Yang teaches that the scrub machine performs a write back process for the selected address and for data and its corresponding ECC read from the memory array (see par. 0046 and 0050). Yang teaches that the scrub machine buffers the corrected data (see par. 0052). Yang teaches that the external data is a first input to a multiplexer (325) and the corrected data is a second input to the multiplexer wherein the multiplexer controls whether new data (externally provided 258) or corrected data (333) should be feed to memory data bus (230) to be written to the memory array (see fig. 3 and par. 0042 et seq.). Yang fails to specifically teach a register and the steps to move data stored in an address in a memory array to a register; however, this teaching is obvious to the teachings of Yang since Yang teaches that a method and an apparatus for eliminating disturb errors in an SMT MRAM comprises a step of transferring data and its corresponding ECC data from a memory array based on a specific requested memory address to a decoder for processing and then to scrub machine scrub wherein the scrub machine produces scrubbed data that are written back to the memory array. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of eliminating disturb errors by substituting the decoder of Yang with the claimed register because Yang teaches that a method for eliminating disturb errors in a SMT MRAM memory includes a scrub machine producing scrubbed output data based on input data received that was transferred to the decoder from the memory array. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for eliminating disturb errors using a scrub machine as taught by Yang (see par. 0075). As per claims 2 and 3, Yang teaches that an error flag accumulator is incremented to maintain the number of errors detected within the data and the number of errors detected within the selected location is compared (see par/ 0052). Yang teaches that if the number of errors is greater than the scrub threshold value then the address of the selected location is regenerated, and the corrected data is written to the selected area in the SMT MRAM array. Yang also teaches that during the regeneration of the address, the corrected data is rewritten (“overwriting”) to the selected memory location (see par. 0052). Allowable Subject Matter Claims 4 to 7 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8 to 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record, teaches a method and an apparatus for eliminating disturb errors of a memory using an error check and scrub system as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “update the latches based on a write operation that occurs while scrubbing the first data; and overwrite, using the scrubbed data as based on a state of the updated latches, at least a portion of the first data” (claim 8). The prior art made of record, fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “write new data to the page in the memory array during the scrubbing; and update a portion of the page in the memory array using the scrubbed data; wherein the page is copied during a first scrubbing operation” (claim 14). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rooney et al. (USPAP 2022/0129348) discloses methods, systems, and apparatuses for a memory device (DRAM) including an error check and scrub (ECS) procedure. Halbert et al. (USPAP 2017/0060681) discloses an error check and scrub (ECS) mode for a memory device. Curley et al. (USP 9,459,997) discloses performing a memory scrubbing operation that includes injection an error on a write operation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Shelly A Chase/Primary Examiner, Art Unit 2112
Read full office action

Prosecution Timeline

Jul 24, 2024
Application Filed
Dec 08, 2025
Non-Final Rejection mailed — §103
Mar 09, 2026
Response Filed
May 20, 2026
Final Rejection mailed — §103
Jul 20, 2026
Response after Non-Final Action
Aug 19, 2026
Request for Continued Examination
Aug 20, 2026
Response after Non-Final Action
Sep 17, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+2.6%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 768 resolved cases by this examiner. Grant probability derived from career allowance rate.

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