DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Response to Amendment
The rejection of claims 1 to 2, 6 and 7 under 35 USC 103 as being unpatentable over Bain et al. is maintained.
The rejection of claims 14 to 16 under 35 USC 103 as being unpatentable over CHA et al. is maintained.
Response to Arguments
Applicant's arguments filed3-9-2026 have been fully considered but they are not persuasive. In response to the arguments concerning the previously rejected claims the following comments are made: Applicant states that the prior art fails to teach using a scrub loop associated with one or more memory arrays;” however this limitation is not claimed, thus applicant is arguing unclaimed subject matter. The examiner would like to point out that the prior art made of record is obvious to the claimed invention because the prior art teaches a scrubbing process using an error checking and scrubbing (ECS) logic and covers the claimed limitation under the broadest reasonable interpretation of the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 2 and 6 to 7 are rejected under 35 U.S.C. 103 as being unpatentable over Bains et al. (USPAP 2024/0211344).
Claim 1:
Bains substantially teaches the claimed invention. Bains teaches a method and an apparatus for internal error scrubbing of a memory subsystem using an adaptable error checking and scrubbing (ECS) engine. Bains teaches that the ECS engine operates based on a scrub rate and a scrub target address (see par. 0037). Bains teaches that the ECS engine is located on a memory die and is part of the memory sub-system (see par. 0037).
Bains teaches that a memory sub-system comprising a memory controller (320) and interfaces with a memory (330) having a plurality of memory cells (see fig. 3 and par. 0074). Bains teaches that the memory controller manages and access data of the memory through a command logic that generates and sends command to the memory (see par. 0075-0076). Bains teaches that the memory controller can set a mode via a register within the memory to trigger the memory to generate addresses and the memory controller controls the execution of a scrub operation (see par. 0077). Bains teaches that based on error patterns detected, it would indicate a row hammer condition, wherein the memory controller may suggest addresses for memory to consider ECS operations (see par. 0078). Bains teaches that the ECS control (326) located within the memory controller applies the error scrubbing operation to the memory based on provided suggested addresses (see par. 0079).
Bains teaches that the memory includes an array (340) which represents locations where data are stored in the memory device. Bains teaches that the array can be organized as banks or bank groups and each address location of the array includes data and associated error correction code (ECC) bits (see par. 0083). Bains teaches in another example that the corrected data is written back to the memory after scrubbing (see par. 0038).
Bains fails to specifically teach the limitation of: “write at least a portion of the scrubbed data to the address in the memory array;” however, this teaching is obvious to the teachings of Bains since, Bains teaches that a method for effectively avoiding the creation of uncorrectable errors includes memory scrubbing using an ECS engine of the memory controller that is adaptable in scrub rate and target addresses and performs a write back of corrected data to the memory.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Bains to include the limitation of: “write at least a portion of the scrubbed data to the address in the memory array” into the invention of Bains because Bains teaches an internal memory scrubbing operation that includes an ECS system writing data back to the array every time, whether or not the ECC detected and corrected an error. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a system for effectively avoiding uncorrectable errors by writing data back to the memory array every time as taught by Bains (see par. 0031 and 0044).
As per claim 2, Bains in one example, teaches an ECS address counters increments addresses for ECS commands and in one example an address control (120) includes a counter to increment the column address for a row or other segment for an ECS operation; which reads on “wherein an error check and scrub (ECS) counter points to the address in the memory array (see par. 0040 and 0042). Bains also teaches that in one example an ECS updates a scrub count and increments the address and continues with the ECS operation (see par. 0125). Bains teaches that the scrubbing operation includes writing to memory and a host to write the data back to the memory (see par. 0038).
As per claim 6, Bains teaches that an ECS engine of a controller performs an error check and scrub operation that is based on commands received and addresses received to apply a scrubbing operation (see par. 0036). Bains also teaches that an automatic or manual scrubbing techniques can be applied to reduce the number of uncorrectable bits in the memory (see par. 0075 et seq.).
As per claim 7, Bains teaches that the memory subsystem performs a refresh operation (“second memory management command”) wherein the memory is put into a self-refresh mode and an automatic ECS operation is performed (see par. 0070). Bains further teaches that scrubbing the data includes storing error information followed by a writing the corrected data back to memory (see par. 0038).
Claims 14 to 16 are rejected under 35 U.S.C. 103 as being unpatentable over CHA et al. (USPAP 2021/0208965 A1).
Claim 14:
CHA substantially the claimed invention. CHA teaches a method of operating a semiconductor memory device including a memory cell array and includes an error correction code (ECC) circuit and a scrubbing control logic. CHA teaches that the semiconductor memory comprises a column address latch (250) supplying addresses to an input/output gaiting circuit (290) having a plurality of read data latches. CHA teaches that the read data latches stores data that is output from the first through eighth bank arrays (310 380) (see par. 0060 and 0062).
CHA teaches that the data in the read data latches are codeword (CW) that is forward to the memory controller (100) for processing (see par. 0063). CHA teaches That the main data (MD) to be written in one bank array of the first through eight bank arrays may be provided to the data I/O buffer (295) (“temporary storage location”) from the memory controller (see par. 0064). CHA teaches that the I/O buffer provides the main data in a write operation from the memory controller to the ECC circuit and when the command CMD corresponds to a read command, the ECC circuit may provide a corrected main data to the I/O buffer (see par. 0065 and 0138). CHA also teaches that the ECC circuit performs selective scrubbing operation to write back a codeword including a correctable error bit in a corresponding memory location (see par. 0138).
CHA teaches that the semiconductor includes a memory cell array (300) having first through eighth bank arrays that includes a plurality of memory cells (see 0053). CHA teaches the semiconductor memory device includes a control logic circuit (210) and coupled to a memory controller (100) (see fig. 1 and par. 0042). CHA teaches that the semiconductor memory device comprises a scrubbing control circuit (500) generating a scrubbing address such that a scrubbing operation is performed on a first memory cell row of a plurality of memory cell rows whenever a refresh operation is performed on the plurality of memory cells (see par. 0048).
CHA does not specifically teach the limitation of write new data to the page in the memory array during the scrubbing; however, this teaching is obvious to the teaching of CHA since, CHA teaches scrubbing the main data stored in the memory array using a refresh operation and writing back some codewords based on the error information wile a refresh operation is performed (see par. 0009).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of CHA to include the steps of: “write a new data to the page in the memory array during the scrubbing” into the invention of CHA because CHA teaches a semiconductor memory device comprising a refresh operation for scrubbing main data and writing back some codewords based on the error information may reduce scrubbing period. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for reducing scrubbing period by using a selective write back operation as taught by CHA (see par. 0009).
As per claim 15, CHA teaches that the data read and written back to a page of the memory cell is a codeword (see par. 0008 and 0048).
As per claim 16, CHA teaches that the memory controller exchanges main data MD with the semiconductor memory and the main data and its respective parity data are stored in a sub-page of the target page (“source page”) in one bank array (see par. 0045 and 0064). CHA teaches that the scrubbed data is written from the I/O buffer to a corresponding memory location (“page”) (see par. 0138).
Allowable Subject Matter
Claims 3 to 5 and 17 to 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8 to 13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record, teaches a method and an apparatus for scrubbing data stored in a memory array and writing back correctable data to the targeted memory cell of the memory array as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “update the latches based on a write operation that occurs while scrubbing the first data; and overwrite, using the scrubbed data and based on a state of the updated latches, at a portion of the first data.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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