Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 8, 9, 11-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
For claim 11-19 the primary reference Matsuno does not teach expanding the gate line holes in claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et al. (US 20220254728 A1) hereafter referred to as Matsuno in view of Tiwari et al. (US 20210217761 A1) hereafter referred to as Tiwari
In regard to claim 1 Matsuno teaches a semiconductor device [see Figs. 1-19D “Referring to FIG. 1, an exemplary semiconductor die 1000 including multiple three-dimensional memory array regions and multiple inter-array regions is illustrated”], comprising:
at least one array [“each of which includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a respective inter-array region 200”] region;
at least one connection [in the “inter-array region 200” see for example “Layer contact via structures 86 can be formed by depositing the at least one conductive material in the contact via cavities”] region; and
a protection structure [“Each contiguous combination of a second-tier backside opening 173 and a first-tier backside opening 171 constitutes an inter-tier backside opening, which is also referred to as a backside opening 177” “The discrete backside openings 177 are laterally expanded and are merged with each other at levels of the continuous insulating layers (132L, 232L) and the sacrificial material layers (142L, 242L) to form a respective backside trench 179” “A backside cavity is present in the portion of each backside trench 179 that is not filled with the continuous metallic material layer”] adjacent the at least one array region and the at least one connection region, wherein the protection structure has a surface comprising [see Fig. 19B “Referring to FIGS. 14A-14D, the backside openings 177 in each cluster are merged (i.e., connected to each other) by widening the backside openings 177, and the moat-region openings 277 in each cluster are also optionally merged (i.e., connected to each other) by widening the moat-region openings 277” “The discrete openings in the continuous insulating layers comprise first discrete openings (such as the backside trenches 179), each of which comprises a pair of laterally undulating sidewalls that generally extend along the first horizontal direction hd1 and having a lateral undulation along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 and comprising multiple vertically straight and laterally convex sidewall segments that are adjoined to each other”] a series of curved portions connected together,
but does not show surrounding in Fig. 19B.
However see Tiwari Fig. 11 “Operative memory-cell pillars 53 are shown as being arranged in a horizontal pattern 67 (e.g., a 2D lattice that may be Bravais or non-Bravais, with an example Bravais rectangular lattice being shown)” “By way of example only, dummy pillars 75 are shown as extending in a single row and/or single column with respect to each of lateral edges 68 and longitudinal ends 70 of horizontal pattern 67, and in one embodiment completely horizontally encircling horizontal pattern 67” “Memory array 12 comprises at least one dummy structure 75a that is a horizontally-elongated wall 75a. In one such embodiment and as shown, dummy structure/wall 75a completely encircles horizontal pattern 67. FIGS. 10 and 11 also show an example embodiment wherein individual memory blocks 58 comprise only one dummy structure 75a in the at least one of the (a) and the (b) (e.g., only one wall per at least one side 68 or at least one end 70)” “in one embodiment, dummy structure 75 comprises insulative material and in one embodiment comprises conductive material”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Matsuno to include completely horizontally encircling i.e. surrounding in the edge of 100, 200, 100 of Matsuno.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide maximum protection for the memory of Matsuno.
In regard to claim 2 Matsuno and Tiwari as combined teaches wherein the protection structure extends along a first direction [vertical “Each contiguous combination of a second-tier backside opening 173 and a first-tier backside opening 171 constitutes an inter-tier backside opening, which is also referred to as a backside opening 177”], and the at least one array region is adjacent to the at least one connection region in a second direction [horizontal] perpendicular to the first direction, and wherein the semiconductor device comprises a stack of conductive layers [ “A semiconductor material layer 110 and a first vertically alternating sequence of first continuous insulating layers 132L and first continuous sacrificial material layers 142L can be formed thereabove” “Referring to FIG. 7, a second vertically alternating sequence of second continuous insulating layers 232L and second continuous sacrificial material layers 242L can be formed” “A plurality of backside recesses (143, 243) may be formed in the volumes from which the material of the continuous sacrificial material layers (142L, 242L) is removed” “Thus, the first and second continuous sacrificial material layers (142L, 242L) may be replaced with the first and second electrically conductive layers (146, 246), respectively”] and insulating layers alternating with each other along the first direction.
In regard to claim 3 Matsuno and Tiwari as combined teaches wherein the conductive layers and the insulating layers in the stack are located along the first direction within a range [see “Each contiguous combination of a second-tier backside opening 173 and a first-tier backside opening 171 constitutes an inter-tier backside opening, which is also referred to as a backside opening 177”] defined by a length of the protection structure along the first direction.
In regard to claim 4 Matsuno and Tiwari as combined teaches wherein the protection structure extends from a first side of the semiconductor device [see Matsuno Fig. 19B see combination surrounding in the edge of 100, 200, 100 of Matsuno] to a second side the semiconductor device along the first direction, the first side and the second side being opposite to each other along the first direction.
In regard to claim 5 Matsuno and Tiwari as combined teaches wherein the protection structure comprises segments that are connected and enclose [see Matsuno Fig. 19B see combination surrounding in the edge of 100, 200, 100 of Matsuno] the at least one array region and the at least one connection region in a plane perpendicular to the first direction.
In regard to claim 6 Matsuno and Tiwari as combined teaches wherein the segments comprise: a first segment and a second segment that each extend along the second direction [see Matsuno Fig. 19B see combination surrounding in the edge of 100, 200, 100 of Matsuno, see that a rectangle has four sides]; and a third segment and a fourth segment that each extend along a third direction perpendicular to the first direction and the second direction.
In regard to claim 7 Matsuno and Tiwari as combined teaches wherein a cross section of at least one of the segments has a shape of partial circles arranged in a line and connected [see 177 in Matsuno Fig. 19B ] together, and wherein the cross section is perpendicular to the first direction.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et al. (US 20220254728 A1) hereafter referred to as Matsuno in view of Tiwari et al. (US 20210217761 A1) hereafter referred to as Tiwari
In regard to claim 10 Matsuno teaches a method [see Figs. 1-19D “Referring to FIG. 1, an exemplary semiconductor die 1000 including multiple three-dimensional memory array regions and multiple inter-array regions is illustrated”], comprising:
providing a semiconductor structure comprising at least one array region [“each of which includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a respective inter-array region 200”] and at least one connection [in the “inter-array region 200” see for example “Layer contact via structures 86 can be formed by depositing the at least one conductive material in the contact via cavities”] region; and
forming a seal ring structure [“Each contiguous combination of a second-tier backside opening 173 and a first-tier backside opening 171 constitutes an inter-tier backside opening, which is also referred to as a backside opening 177” “The discrete backside openings 177 are laterally expanded and are merged with each other at levels of the continuous insulating layers (132L, 232L) and the sacrificial material layers (142L, 242L) to form a respective backside trench 179” “A backside cavity is present in the portion of each backside trench 179 that is not filled with the continuous metallic material layer”] adjacent the at least one array region and the at least one connection region, wherein the seal ring structure has a surface comprising [see Fig. 19B “Referring to FIGS. 14A-14D, the backside openings 177 in each cluster are merged (i.e., connected to each other) by widening the backside openings 177, and the moat-region openings 277 in each cluster are also optionally merged (i.e., connected to each other) by widening the moat-region openings 277” “The discrete openings in the continuous insulating layers comprise first discrete openings (such as the backside trenches 179), each of which comprises a pair of laterally undulating sidewalls that generally extend along the first horizontal direction hd1 and having a lateral undulation along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 and comprising multiple vertically straight and laterally convex sidewall segments that are adjoined to each other”] a series of curved portions connected together
but does not show surrounding in Fig. 19B.
However see Tiwari Fig. 11 “Operative memory-cell pillars 53 are shown as being arranged in a horizontal pattern 67 (e.g., a 2D lattice that may be Bravais or non-Bravais, with an example Bravais rectangular lattice being shown)” “By way of example only, dummy pillars 75 are shown as extending in a single row and/or single column with respect to each of lateral edges 68 and longitudinal ends 70 of horizontal pattern 67, and in one embodiment completely horizontally encircling horizontal pattern 67” “Memory array 12 comprises at least one dummy structure 75a that is a horizontally-elongated wall 75a. In one such embodiment and as shown, dummy structure/wall 75a completely encircles horizontal pattern 67. FIGS. 10 and 11 also show an example embodiment wherein individual memory blocks 58 comprise only one dummy structure 75a in the at least one of the (a) and the (b) (e.g., only one wall per at least one side 68 or at least one end 70)” “in one embodiment, dummy structure 75 comprises insulative material and in one embodiment comprises conductive material”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Matsuno to include completely horizontally encircling i.e. surrounding in the edge of 100, 200, 100 of Matsuno.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide maximum protection for the memory of Matsuno.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuno et al. (US 20220254728 A1) hereafter referred to as Matsuno in view of Tiwari et al. (US 20210217761 A1) hereafter referred to as Tiwari
In regard to claim 20 Matsuno teaches a memory system [see Figs. 1-19D “Referring to FIG. 1, an exemplary semiconductor die 1000 including multiple three-dimensional memory array regions and multiple inter-array regions is illustrated”], comprising:
a memory device [“each of which includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a respective inter-array region 200”]; and
a memory controller [“Semiconductor devices 720 can be formed on a substrate semiconductor layer 9, which is provided at least within an upper portion of a substrate 8” “semiconductor devices 720 may include field effect transistors that are formed over a top surface of the substrate 8” “semiconductor devices in the underlying semiconductor devices 720 may comprise word line switch devices configured to control a bias voltage to respective word lines, and/or bit line driver devices, such as sense amplifiers”] coupled to the memory device and configured to control the memory device, wherein the memory device comprises:
at least one array [“each of which includes two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by a respective inter-array region 200”] region;
at least one connection [in the “inter-array region 200” see for example “Layer contact via structures 86 can be formed by depositing the at least one conductive material in the contact via cavities”] region; and
a protection structure [“Each contiguous combination of a second-tier backside opening 173 and a first-tier backside opening 171 constitutes an inter-tier backside opening, which is also referred to as a backside opening 177” “The discrete backside openings 177 are laterally expanded and are merged with each other at levels of the continuous insulating layers (132L, 232L) and the sacrificial material layers (142L, 242L) to form a respective backside trench 179” “A backside cavity is present in the portion of each backside trench 179 that is not filled with the continuous metallic material layer”] adjacent the at least one array region and the at least one connection region, wherein the protection structure has a surface [see Fig. 19B “Referring to FIGS. 14A-14D, the backside openings 177 in each cluster are merged (i.e., connected to each other) by widening the backside openings 177, and the moat-region openings 277 in each cluster are also optionally merged (i.e., connected to each other) by widening the moat-region openings 277” “The discrete openings in the continuous insulating layers comprise first discrete openings (such as the backside trenches 179), each of which comprises a pair of laterally undulating sidewalls that generally extend along the first horizontal direction hd1 and having a lateral undulation along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1 and comprising multiple vertically straight and laterally convex sidewall segments that are adjoined to each other”] comprising a series of curved portions connected together
but does not show surrounding in Fig. 19B.
However see Tiwari Fig. 11 “Operative memory-cell pillars 53 are shown as being arranged in a horizontal pattern 67 (e.g., a 2D lattice that may be Bravais or non-Bravais, with an example Bravais rectangular lattice being shown)” “By way of example only, dummy pillars 75 are shown as extending in a single row and/or single column with respect to each of lateral edges 68 and longitudinal ends 70 of horizontal pattern 67, and in one embodiment completely horizontally encircling horizontal pattern 67” “Memory array 12 comprises at least one dummy structure 75a that is a horizontally-elongated wall 75a. In one such embodiment and as shown, dummy structure/wall 75a completely encircles horizontal pattern 67. FIGS. 10 and 11 also show an example embodiment wherein individual memory blocks 58 comprise only one dummy structure 75a in the at least one of the (a) and the (b) (e.g., only one wall per at least one side 68 or at least one end 70)” “in one embodiment, dummy structure 75 comprises insulative material and in one embodiment comprises conductive material”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Matsuno to include completely horizontally encircling i.e. surrounding in the edge of 100, 200, 100 of Matsuno.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide maximum protection for the memory of Matsuno.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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