Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. The title “DISPLAY PANEL AND DISPLAY DEVICE” is too broad and generic and does not clearly indicate the subject matter. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections.
Claims 1 and 20 are objected to because of the following informalities: for example, these claims recite the limitations “the initial output signal of an xth stage shift register…1≤x≤N, and 1≤y≤N.” The claim language is unclear because it does not specify any definite relationship/association between x and y. Appropriate correction is required. The dependent claims are also objected to for the same reasons.
Claims 2-3 are objected to because of the following informalities: for example, the claims recite the limitations pulse change frequency of F0/F1…F0 ≠ F1…F0 > F1.” First, the terms “pulse change frequency” is not clearly defined in the claims and the meaning is ambiguous in the display driving circuit because it is unclear what characteristics is being measure. Second, the frequencies are compared without the clear boundary or measurement basis. Appropriate correction is required.
Claim 20 is objected to under 37 CFR 1.75 as being dependent upon claim 1 but failing to further limit the subject matter of the claim from which it depends. For example, claim 20 merely recites a “display device” comprising the display panel of claim 1 without positively reciting any additional structure or functional limitations of the display device beyond those already recited in claim 1. Therefore, this claim does not add any patentable distinction over claim 1 and is therefore objected to as being an improper dependent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (2016/0064098).
Regarding claim 1, Han teaches a display panel (Han: abstract, and para 0056, a display device), comprising: a drive circuit, wherein the drive circuit comprises N cascaded stages of shift registers (Han: para 0050-0055, a shift register including multi-level shift register units), wherein N ≥ 2 (Han: Figs. 1A-1B and 2A-2B and para 0189,
“S1, S2 . . . , Sn . . . SN represent a first level shift register unit, a second level shift register unit . . . an n-th level shift register unit . . . an N-th level shift register unit respectively.”); a shift register of the N cascaded stages of shift registers comprises a control unit (Han: abstract, Figs. 1A-1B and 2A-2B and para 0078-0085, first control module and second control module correspond to a control unit of claim 1. Carry output module corresponds to initial output unit of claim 1. Shift output module corresponds to first output unit), an initial output unit and a first output unit (Han: abstract, Figs. 1A-1B and 2A-2B and para 0078-0085, first control module and second control module correspond to a control unit of claim 1. Carry output module corresponds to initial output unit of claim 1. Shift output module corresponds to first output unit); wherein the control unit is configured to at least receive an input signal and control a signal of a first output node and a signal of a second output node (Han: abstract, Figs. 1A-1B and 2A-2B and para 0078-0085, first control module transmits a start signal to first node Q1 and second control module pulls potential of second node Q2 to a potential different from the first node); the initial output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control an initial output signal (Han: abstract, Figs. 1A-1B and 2A-2B and para 0078-0085, carry output module outputs a carry signal output end OUT_C(n) on the basis of the potential of the first node Q1 and the potential of the second node Q2); the initial output signal of an xth stage shift register is the input signal of a yth stage shift register, 1≤x≤N, and 1≤y≤N (Han: Figs. 2A-2B and 4A-4B and para 0190-0195, “except for the first level shift register unit…start signal input of each level is connected to the carry signal output end of a previous level” and “OUT_C(N)…connected to input end STV…of the next level.”); and the first output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control a first output signal (Han: Figs. 2A-2B and 4A-4B and para 0018 and 0150-0165, shift output module outputs a shift signal based on the potentials of first node Q1 and second node Q2).
Regarding claim 4, Han teaches wherein the initial output unit comprises a
first initial output module and a second initial output module (Han: Figs. 2A-2B and 4A-4B and para 0022, a first carry output transistor and a second carry output transistor); the first initial output module (Han: Figs. 2A-2B and 4A-4B and para 0138-0145, first carry output transistor T631) is configured to at least receive an initial output control signal (Han: para 0120-0130, second clock signal output end) and the signal of the first output node (Han: Figs. 2A-2B and 4A-4B and para 0138-0145), and control the initial output signal (Han: Figs. 2A-2B and 4A-4B and para 0138-0145, carry signal output end OUT_C(n)); and the second initial output module (Han: Figs. 2A-2B and 4A-4B and para 0097-0100, a second carry output transistor T332) is configured to at least receive a first voltage signal (Han: Figs. 2A-2B and 4A-4B and para 0130-0140, first low level supply LVGL) and the signal of the second output node, and control the initial output signal (Han: Figs. 2A-2B and 4A-4B and para 0138-0145, carry signal output end OUT_C(n)).
Regarding claim 20, this claim is similarly rejected based on the same rationale as claim 1 (as discussed above, Han clearly teaches a display device including the above-discussed shift register and lists examples including a display device at para 0005-0013 and describes the gate driving and scanning circuitries).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Cho et al. (2021/0110774).
Regarding claim 2, Han teaches the two outputs per stage (Han: OUT_C(n) and OUT(n)). Han does not explicitly teach the concept of wherein the initial output signal has a pulse change frequency of F0, and the first output signal has a pulse change frequency of F1; wherein within at least a part of a time period of a working process of the display panel, F0 ≠ F1. Cho teaches wherein the initial output signal has a pulse change frequency of F0, and the first output signal has a pulse change frequency of F1; wherein within at least a part of a time period of a working process of the display panel, F0 ≠ F1 (Cho: para 0050-0060 and 0107-0110, the carry signal CR that is provided as the input signal SIN for the next stage is discussed. Also, the masking control unit 130 may output the scan signal SS having the off level when the masking signal MS has the off level, or may not output the scan signal SS having the on level. Stages output scan signals in FP1 and FP3, but not in FP2 and FP4 provide a driving frequency such as 30 Hz, which is lower than normal 60 Hz.).
They are analogous art because they deal with the same field of invention of a display device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s shift register in view of the teachings of Cho so as to obtain variable scan output frequency during the scanning operation and to provide the benefits such as reduction of power consumption (para 0003).
Regarding claim 3, the combination teaches wherein within at least a part of the time period of the working process of the display panel, F0 > F1 (Han: abstract, Figs. 1A-1B and 2A-2B and para 0078-0085, Cho: para 0050-0060 and 0107-0110, as discussed above, output in FP1 and FP3 but not FP2 and FP4).
Allowable Subject Matter
Claims 5-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the objections to the claims and the specification.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/SEJOON AHN/ Primary Examiner, Art Unit 2628