DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 5/16/24. It is noted, however, that applicant has not filed a certified copy of the Chinese application CN202410608741.1 as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 15, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu, CN 114283689
Regarding claim 1, Wu discloses a display panel, comprising a display area and a border area that surrounds the display area (Fig. 8; display area 10, non-display area 20), wherein the display area comprises a data signal line (Fig. 8; Data line D), and the border area comprises a test signal line and a common voltage signal line (Fig. 8; signal line 50, signal line 40 is input with a common voltage in one instance and is therefore considered a common voltage signal line), which extend around the display area (Fig.8; signal line 50, line 40 are around the display area ); and the test signal line is configured to: be electrically connected to the data signal line and be input with a test signal during a test stage of the display panel (Fig. 8; signal line 50 transmits data signal in a test stage); and be electrically connected to the common voltage signal line and be input with a first common voltage signal or output a second common voltage signal on the common voltage signal line during a use stage of the display panel (Fig. 8;signal line 50 is connected to line 40 through distributer 120; signal line 50 transmits the common voltage signal in a display stage).
Regarding claim 15, Wu discloses a method for preparing a display panel, comprising: preparing the display panel including a display area and a border area that surrounds the display area (Fig. 8; display area 10, non-display area 20), the display area comprising a data signal line (Fig. 8; Data line D), and the border area comprising a test signal line and a common voltage signal line (Fig. 8; signal line 50, signal line 40 is input with a common voltage in one instance and is therefore considered a common voltage signal line), which extend around the display area (Fig.8; signal line 50, line 40 are around the display area ); electrically connecting the test signal line with the data signal line, and inputting a test signal into the test signal line to test the display panel (Fig. 8; signal line 50 transmits data signal in a test stage); and electrically connecting the test signal line with the common voltage signal line (Fig. 8;signal line 50 is connected to line 40 through distributer 120).
Regarding claim 17, Wu discloses controlling the test signal line to be electrically connected to the data signal line, and inputting a test signal into the test signal line during a test stage of the display panel; controlling the test signal line to be electrically connected to the common voltage signal line, and inputting a first common voltage signal into the test signal line or outputting a second common voltage signal on the common voltage signal line through the test signal line during a use stage of the display panel ( Fig. 8; signal line 50 transmits data signal in test stage and common voltage signal in a use stage).
Regarding claim 20, Wu discloses a display device, comprising a display panel that comprises a display area and a border area surrounding the display area (Fig. 8; display area 10, non-display area 20), wherein the display area comprises a data signal line (Fig. 8; Data line D), and the border area comprises a test signal line and a common voltage signal line (Fig. 8; signal line 50, signal line 40 is input with a common voltage in one instance and is therefore considered a common voltage signal line), which extend around the display area (Fig.8; signal line 50, line 40 are around the display area ); and the test signal line is configured to: be electrically connected to the data signal line and be input with a test signal during a test stage of the display panel (Fig. 8; signal line 50 transmits data signal in a test stage); and be electrically connected to the common voltage signal line and be input with a first common voltage signal or output a second common voltage signal on the common voltage signal line during a use stage of the display panel (Fig. 8;signal line 50 is connected to line 40 through distributer 120; signal line 50 transmits the common voltage signal in a display stage).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu, CN 114283689 in view of Zou et al., CN 107025867
Regarding claim 3, Wu is silent wherein the border area further comprises a first gating circuit and a first control signal line, the first gating circuit being electrically connected to the first control signal line, the test signal line and the common voltage signal line each; and the first control signal line and the first gating circuit are configured so that: during the test stage of the display panel, the first control signal line receives an inactive level signal, and the first gating circuit controls the test signal line and the common voltage signal line to be disconnected according to the inactive level signal; and during the use stage of the display panel, the first control signal line receives an active level signal, and the first gating circuit controls the test signal line and the common voltage signal line to be connected according to the active level signal. Zou teaches border area further comprises a first gating circuit and a first control signal line, the first gating circuit being electrically connected to the first control signal line, the test signal line and the common voltage signal line each; and the first control signal line and the first gating circuit are configured so that: during the test stage of the display panel, the first control signal line receives an inactive level signal, and the first gating circuit controls the test signal line and the common voltage signal line to be disconnected according to the inactive level signal; and during the use stage of the display panel, the first control signal line receives an active level signal, and the first gating circuit controls the test signal line and the common voltage signal line to be connected according to the active level signal (Fig. 1; gate driving circuit 130 to common voltage lines J1, J2 ). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Zou into Wu for the benefit of providing a circuit for testing the multiple pixels on the display.
Regarding claim 12, Wu is silent in wherein a quantity of the test signal lines is at least two; and each of the test signal lines is electrically connected to the common voltage signal line through at least one connection position, and the test signal lines that are different have different connection positions on the common voltage signal line. Zou teaches wherein a quantity of the test signal lines is at least two; and each of the test signal lines is electrically connected to the common voltage signal line through at least one connection position, and the test signal lines that are different have different connection positions on the common voltage signal line (Fig. 1; voltage lines J1 and J2). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Zou into Wu for the benefit of providing a circuit for testing the multiple pixels on the display.
Allowable Subject Matter
Claim 2, 4-11, 13, 14, 16, 18, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/FEBA POTHEN/Examiner, Art Unit 2858
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