Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of a claim for foreign priority to application CN202310926371.1 under 35 U.S.C. § 119(a)-(d) or (f).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: element. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 cites “unit regions” and “unit sub-regions” but fails to define them in terms of physical or functional structure. The specification only presents the boundaries of such regions with arbitrarily-drawn dashes in Fig. 6. Moreover, claim 4 cites that the grooves “in respective sub-regions are different in size” and Applicant defines “size” in a volumetric fill-ratio manner. One skilled in the art could draw the unit sub-region boundary differently and arrive at different “size” ratios.
For the purpose of examination, Examiner interprets grooves “different in size” to be grooves with differing widths and/or depths, thus enabling “unit sub-regions” to remain arbitrary in dimension.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-7, 10-12, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kotani et al., US 2018/0068923 A1 (hereinafter Kotani) in view of Bader et al., US 2023/0062922 A1 (hereinafter Bader).
Regarding claim 1, Kotani discloses: A substrate structure (Kotani, semiconductor device [para. 67, Fig. 1]), comprising: a base substrate (Kotani, substrate 10 [para. 68, Fig. 8B]); an insulation layer and a growth substrate on the base substrate in sequence (Kotani, “a nucleation layer…an electron transit layer 21 are sequentially formed on a substrate 10” [para. 68, Fig. 8A]); and grooves in a side of the base substrate away from the growth substrate (Kotani, “groove 71 is formed from a back surface 10a (bottom surface in the figure) of the substrate 10” [para. 69, Fig. 8B]), wherein the grooves each penetrate at least one part of the base substrate (Kotani, “Thereafter, part of the substrate 10…is removed to form the groove 71” [para. 69]). Kotani does not disclose grooves of differing depth or opening width.
However, Bader, in the same field of endeavor, teaches a substrate structure wherein at least two of the grooves are different in depth or opening width (Bader, “first trench 154 has a first width, W1, and a first height, H1. A second trench 156 is in the substrate 152B. The second trench 156 has a second width, W2, and a second height, H2” [para. 48, Fig. 1E]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kotani with the teachings of Bader, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Bader, to optimize performance in various device/circuit regions with different functionality (Bader, para. 36). This obvious combination is hereinafter referred to as modified Kotani.
Regarding claim 5, Kotani further discloses a substrate structure: wherein one of the grooves comprises a first portion in the base substrate, a second portion in the insulation layer, and a third portion in the growth substrate (Kotani, “Thereafter, part of the substrate 10, the buffer layer 11, and the electron transit layer 21 in the opening of the resist pattern is removed to form the groove 71 [para. 69]); wherein an opening width of the first portion of the groove is greater than an opening width of the second portion and an opening width of the third portion of the groove (Kotani, Fig. 8B).
Regarding claim 6, Kotani further discloses a substrate structure wherein the opening widths of the first portion, the second portion and the third portion of the groove gradually decrease (Kotani, Fig. 8B).
Regarding claim 7, Kotani further discloses a substrate structure wherein one of the grooves penetrates the base substrate and the insulation layer, and the groove penetrates a part of the growth substrate (Kotani, “Thereafter, part of the substrate 10, the buffer layer 11, and the electron transit layer 21 in the opening of the resist pattern is removed to form the groove 71” [para. 69], Fig. 8B).
Regarding claim 10, Kotani further discloses a substrate structure comprising a heat-dissipation layer covering the inner wall of the grooves (Kotani, heat dissipation layer 53, Fig. 9B).
Regarding claim 11, Kotani further discloses a semiconductor structure (Kotani, semiconductor device [para. 42]), comprising: the substrate structure according to claim 1 (modified Kotani); and a device structure on the substrate structure, wherein the device structure is on a side of the growth substrate away from the base substrate (Kotani, “a gate electrode 31, a source electrode 32, and a drain electrode 33 formed on the barrier layer 22” [para. 42]); and wherein the semiconductor structure is any one of a high electron mobility transistor device, a vertical power device, a radio frequency device and a light emitting diode device (Kotani, a GaN-HEMT [para. 42]).
Regarding claim 12, Kotani discloses a method of manufacturing a substrate structure (Kotani, semiconductor device [para. 67, Fig. 1]), comprising: providing a base substrate (Kotani, substrate 10 [para. 68, Fig. 8B]); forming an insulation layer and a growth substrate on the base substrate in sequence (Kotani, “a nucleation layer…an electron transit layer 21 are sequentially formed on a substrate 10” [para. 68, Fig. 8A]); and forming grooves at a side of the base substrate away from the growth substrate (Kotani, “groove 71 is formed from a back surface 10a (bottom surface in the figure) of the substrate 10” [para. 69, Fig. 8B]), wherein the grooves each penetrate at least one part of the base substrate (Kotani, “Thereafter, part of the substrate 10…is removed to form the groove 71” [para. 69]). Kotani does not disclose grooves of differing depth or opening width.
However, Bader, in the same field of endeavor, teaches a method of manufacturing a substrate structure wherein at least two of the grooves are different in depth or opening width (Bader, “first trench 154 has a first width, W1, and a first height, H1. A second trench 156 is in the substrate 152B. The second trench 156 has a second width, W2, and a second height, H2” [para. 48, Fig. 1E]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kotani with the teachings of Bader, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Bader, to optimize performance in various device/circuit regions with different functionality (Bader, para. 36). This obvious combination is hereinafter referred to as modified Kotani method.
Regarding claim 16, Kotani further discloses a method of manufacturing a substrate structure: wherein one of the grooves comprises a first portion in the base substrate, a second portion in the insulation layer, and a third portion in the growth substrate (Kotani, “Thereafter, part of the substrate 10, the buffer layer 11, and the electron transit layer 21 in the opening of the resist pattern is removed to form the groove 71 [para. 69]); wherein an opening width of the first portion of the groove is greater than an opening width of the second portion and an opening width of the third portion of the groove (Kotani, Fig. 8B).
Regarding claim 17, Kotani further discloses a method of manufacturing a substrate structure wherein the opening widths of the first portion, the second portion and the third portion of the groove gradually decrease (Kotani, Fig. 8B).
Regarding claim 18, Kotani further discloses a substrate structure wherein one of the grooves penetrates the base substrate and the insulation layer, and the groove penetrates a part of the growth substrate (Kotani, “Thereafter, part of the substrate 10, the buffer layer 11, and the electron transit layer 21 in the opening of the resist pattern is removed to form the groove 71” [para. 69], Fig. 8B).
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani and modified Kotani method, respectively, as applied to claims 1 and 12 above, and further in view of Koontz et al., US 2014/0264759 A1 (hereinafter Koontz).
Regarding claim 2, Koontz discloses a substrate structure wherein a density of the grooves in a central region of the base substrate is greater than a density of the grooves in an edge region of the base substrate (Koontz, Figs. 1A, 1B, shows channels 120 [heat dissipation
grooves] only in the region between vias 116a and vias 116b [the central region] and not in the region extending horizontally outward from vias 116a and 116b [the edge region], i.e., the distribution density of heat dissipation grooves in the central region is greater than a distribution density of heat dissipation grooves in the edge region).
Furthermore, it is a well-known engineering principle that semiconductor devices generate the highest thermal loads in the center of the die. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to take modified Kotani and use Koontz’s arrangement of cooling channels with a higher density in the central region to optimize thermal management where it is needed most, yielding predictable results (KSR, 550 U.S. at 416).
Regarding claim 14, Koontz discloses a method for manufacturing a substrate structure wherein a density of the grooves in a central region of the base substrate is greater than a density of the grooves in an edge region of the base substrate (Koontz, Figs. 1A, 1B, shows channels 120 [heat dissipation grooves] only in the region between vias 116a and vias 116b [the central region] and not in the region extending horizontally outward from vias 116a and 116b [the edge region], i.e., the distribution density of heat dissipation grooves in the central region is greater than a distribution density of heat dissipation grooves in the edge region).
Furthermore, it is a well-known engineering principle that semiconductor devices generate the highest thermal loads in the center of the die. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to take modified Kotani method and use Koontz’s arrangement of cooling channels with a higher density in the central region to optimize thermal management where it is needed most, yielding predictable results (KSR, 550 U.S. at 416).
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani and modified Kotani method, respectively, as applied to claims 1 and 12 above, and further in view of Jacob et al., US 2018/0026096 A1 (hereinafter Jacob).
Regarding claim 3, Jacob discloses a substrate structure wherein along a direction from a center of the base substrate to an edge of the base substrate, depths and/or opening widths of the grooves gradually decrease (Jacob, “each portion of the trenches 25a, 25b and 25c farthest from the edge 20 can have a depth that is deeper than portions of the respective trenches closest to the edge 20 of the substrate” [para. 29, Fig. 2]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani with the teachings of Jacob, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art would have been motivated to apply this known grading technique to modified Kotani’s heat-dissipation grooves, as “more or less material can be at the center of the substrate to compensate for a convex or concave bowing” (Jacob, para. 25).
Regarding claim 13, Jacob discloses a method of manufacturing a substrate structure wherein along a direction from a center of the base substrate to an edge of the base substrate, depths and/or opening widths of the grooves gradually decrease (Jacob, “each portion of the trenches 25a, 25b and 25c farthest from the edge 20 can have a depth that is deeper than portions of the respective trenches closest to the edge 20 of the substrate” [para. 29, Fig. 2]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani method with the teachings of Jacob, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art would have been motivated to apply this known grading technique to modified Kotani’s heat-dissipation grooves, as “more or less material can be at the center of the substrate to compensate for a convex or concave bowing” (Jacob, para. 25).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani and modified Kotani method, respectively, as applied to claims 1 and 12 above, and further in view of Kuo, US 2023/0307389 A1 (hereinafter Kuo).
Regarding claim 4, Kuo discloses a substrate structure wherein the substrate structure comprises unit regions (Kuo, “the DTC region 120 includes an array of DTC unit cells 210” [para. 36, Fig. 2]), each of the unit regions comprises at least two unit sub-regions (Kuo, “Each DTC unit cell 210 includes four DTC unit groups 212” [para. 36, Fig. 2]), and each of the at least two unit sub-regions comprises at least one of the grooves (Kuo, "Each DTC unit group 212 includes six DTC units 214" [para. 36] wherein the "Three trenches 226-1, 226-2, and 226-3, each corresponding to a DTC unit 214" [para. 39, Figs. 2 and 3]); and in one of the unit regions, the grooves in respective unit sub-regions are different in size (Kuo, “the depth of the trenches 226-1 and 226-6 is D1, while the depth of the trenches 226-2, 226-3, 226-4, and 226-5 is D2, and D1 is smaller than D2. That is, the depth of the outmost trenches (also referred to as “edge trenches”, e.g., 226-1 and 226-6) in the X-direction is smaller than the depth of other trenches (also referred to as “non-edge trenches”, e.g., 226-1 and 226-6)” [para. 47, Fig. 3].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani with the teachings of Kuo, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art organizing the heat-dissipation grooves taught by modified Kotani into a manufacturable layout would have looked to known hierarchical trench-array organizational schemes such as this one and found it obvious to apply the reference's variety of trench size within one unit in heat dissipation groove context, yielding predictable results (KSR, 550 U.S. at 416).
Regarding claim 15, Kuo discloses a method of manufacturing a substrate structure wherein the substrate structure comprises unit regions (Kuo, “the DTC region 120 includes an array of DTC unit cells 210” [para. 36, Fig. 2]), each of the unit regions comprises at least two unit sub-regions (Kuo, “Each DTC unit cell 210 includes four DTC unit groups 212” [para. 36, Fig. 2]), and each of the at least two unit sub-regions comprises at least one of the grooves (Kuo, "Each DTC unit group 212 includes six DTC units 214" [para. 36] wherein the "Three trenches 226-1, 226-2, and 226-3, each corresponding to a DTC unit 214" [para. 39, Figs. 2 and 3]); and in one of the unit regions, the grooves in respective unit sub-regions are different in size (Kuo, “the depth of the trenches 226-1 and 226-6 is D1, while the depth of the trenches 226-2, 226-3, 226-4, and 226-5 is D2, and D1 is smaller than D2. That is, the depth of the outmost trenches (also referred to as “edge trenches”, e.g., 226-1 and 226-6) in the X-direction is smaller than the depth of other trenches (also referred to as “non-edge trenches”, e.g., 226-1 and 226-6)” [para. 47, Fig. 3].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani method with the teachings of Kuo, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art organizing the heat-dissipation grooves taught by modified Kotani method into a manufacturable layout would have looked to known hierarchical trench-array organizational schemes such as this one and found it obvious to apply the reference's variety of trench size within one unit in heat dissipation groove context, yielding predictable results (KSR, 550 U.S. at 416).
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani and modified Kotani method, respectively, as applied to claims 1 and 12 above, and further in view of Yedinak et al., US 2012/0273875 A1 (hereinafter Yedinak).
Regarding claim 8, Yedinak discloses a substrate structure wherein the growth substrate is a superjunction structure (Yedinak, “an N-type epitaxial layer extending over the alternating P-N pillars” [para. 30]), the superjunction structure comprises n-type semiconductor structures and p-type semiconductor structures (Yedinak, “the P-type silicon material in the plurality of trenches forming P-pillars, those portions of the one or more N-type epitaxial layers separating the P-pillars forming N-pillars” [para. 30]), and the n-type semiconductor structures and the p-type semiconductor structures are alternately distributed along a direction parallel to the growth substrate (Yedinak, “the N-pillars and the P-pillars form alternating P-N-pillars” [para. 30]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani with the teachings of Yedinak, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art designing a high-voltage vertical power device using the previously taught heat-dissipating substrate architecture would have had reason to incorporate a superjunction growth substrate, since superjunction structures were a well-established, predictable technique for improving breakdown voltage in exactly this device class. As expressed by Yedinak, in traditional semiconductor substrates, “because of the proportional relationship between the drain-to-source on-resistance Rds-on and the breakdown voltage, improving the voltage performance of the transistor while maintaining a low Rds-on poses a challenge” (Yedinak, para. 4). One of ordinary skill in the art could have applied the known improvement of incorporating a superjunction structure to Applicant’s substrate structure to yield predictable results (KSR, 550 U.S. at 417).
Regarding claim 19, Yedinak discloses a method for manufacturing a substrate structure by forming a superjunction structure in the growth substrate (Yedinak, “an N-type epitaxial layer extending over the alternating P-N pillars” [para. 30]), the superjunction structure comprises n-type semiconductor structures and p-type semiconductor structures (Yedinak, “the P-type silicon material in the plurality of trenches forming P-pillars, those portions of the one or more N-type epitaxial layers separating the P-pillars forming N-pillars” [para. 30]), and the n-type semiconductor structures and the p-type semiconductor structures are alternately distributed along a direction parallel to the growth substrate (Yedinak, “the N-pillars and the P-pillars form alternating P-N-pillars” [para. 30]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani method with the teachings of Yedinak, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. A person of ordinary skill in the art designing a high-voltage vertical power device using the previously taught heat-dissipating substrate architecture would have had reason to incorporate a superjunction growth substrate, since superjunction structures were a well-established, predictable technique for improving breakdown voltage in exactly this device class. As expressed by Yedinak, in traditional semiconductor substrates, “because of the proportional relationship between the drain-to-source on-resistance Rds-on and the breakdown voltage, improving the voltage performance of the transistor while maintaining a low Rds-on poses a challenge” (Yedinak, para. 4). One of ordinary skill in the art could have applied the known improvement of incorporating a superjunction structure to Applicant’s substrate structure to yield predictable results (KSR, 550 U.S. at 417).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani as applied to claim 1 above, and further in view of Henson et al., US 2011/0147885 A1 (hereinafter Henson).
Regarding claim 9, Henson discloses a substrate structure comprising a protective layer on a side of the base substrate away from the growth substrate (Henson, “protective layer 18 can further be formed over the semiconductor device layer 16” [para. 52, Fig. 5]), wherein the protective layer has openings exposing the base substrate, and the openings correspond to the grooves one by one (Henson, “protective layer 18, is patterned to form one or more device regions 2, which are defined by one or more isolation trenches 30” [para. 52, Fig. 6A]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani with the teachings of Henson, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. Henson’s one-to-one groove correspondence is the logical and functionally necessary consequence of using a patterned mask to etch discrete grooves. As disclosed by Henson, one would be motivated to include a surface protection layer as it may “protect layer 16 [semiconductor layer] during planarization” and can “comprise any suitable material(s) that can function as a planarization stop layer” (Henson, para. 45). A person having ordinary skill in the art implementing modified Kotani’s grooves would find it obvious to practice Henson’s express one-to-one correspondence, since a mask patterned to define discrete groove locations necessarily and predictably produces that correspondence.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over modified Kotani method as applied to claim 12 above, and further in view of Henson.
Regarding claim 20, modified Kotani method further discloses forming a heat-dissipation layer covering the inner wall of the grooves (Kotani, heat dissipation layer 53 [Fig. 9B]). Modified Kotani method does not disclose a protective layer functioning as a mask to form the grooves.
However, Henson, in the same field of endeavor, discloses a method of forming a protective layer on the side of the base substrate away from the growth substrate (Henson, “protective layer 18 can further be formed over the semiconductor device layer 16” [para. 52, Fig. 5]); forming openings exposing the base substrate on the protective layer; and etching the base substrate, using the protective layer with the openings as a mask, to form the grooves (Henson, “protective layer 18, is patterned to form one or more device regions 2, which are defined by one or more isolation trenches 30” [para. 52, Fig. 6A]). Henson further discloses that “Patterning of the layered substrate structure 10 can be carried out by first depositing a blanket dielectric hard mask layer (not shown) over the layered substrate structure 10, followed by conventional lithography and etching steps that pattern the layered substrate structure 10, as shown in FIG. 6A” [para. 54].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kotani with the teachings of Henson, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. Henson’s one-to-one groove correspondence is the logical and functionally necessary consequence of using a patterned mask to etch discrete grooves. As disclosed by Henson, one would be motivated to include a surface protection layer as it may “protect layer 16 [the semiconductor layer] during planarization” and can “comprise any suitable material(s) that can function as a planarization stop layer” (Henson, para. 45). A person having ordinary skill in the art implementing modified Kotani’s grooves would find it obvious to practice Henson’s express one-to-one correspondence, since a mask patterned to define discrete groove locations necessarily and predictably produces that correspondence.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GERALD H BISSELL whose telephone number is (571) 272-0834. The examiner can normally be reached Mon - Fri 0800 - 1600.
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/GERALD H. BISSELL/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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