DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of a claim for foreign priority to application KR10-2023-0101894 under 35 U.S.C. § 119(a)-(d) or (f).
Drawings
The drawings are objected to because Figs. 3 and 6 are labeled as cross-sectional views taken along lines II-II'. However, the drawings are labeled with I-I indicators. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informality: claim 5 recites "the base substrate," but claim 1 establishes only "a substrate." There is lack of proper antecedent basis and correction to "a substrate" is suggested.
Claim 7 is objected to because of the following informality: “wherein each of the plurality of sub-active holes have an elongated shape extends from the channel area to the drain area” contains a subject-verb agreement error.
Claim 8 is objected to because of the following informality: “neodium (Nd)” is a misspelling of “neodymium (Nd).”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2013/0043479 A1 (hereinafter Kim) in view of Cho US 2014/0291635 A1 (hereinafter Cho).
Regarding claim 1, Kim discloses: A thin film transistor substrate (Kim, thin film transistor substrate 100 [Para. 0029, Figs. 1-4]), comprising:
a substrate (Kim, substrate 50 [Para. 0029, Fig. 2]);
a thin film transistor on the substrate (Kim, thin film transistor 200 [Para. 0030, Fig. 2]),
wherein the thin film transistor includes:
an active layer (Kim, active layer 270 [Para. 0029, Fig. 2]);
a conductive material layer on the active layer (Kim, "resistive contact layers 271 and 273 may include, for example, amorphous silicon (n+a-Si) doped with n type impurities in high concentration" [Para. 0051, Fig, 2]); and
a gate electrode spaced apart from the active layer and partially overlapping the active layer (Kim, "a laminated structure may be formed in which the gate insulating film 240 is formed on the active layer 270, and the gate electrode 220 is formed on the gate insulating film 240" [Para. 0033, Fig. 2]),
wherein the active layer includes:
a channel area partially overlapping the gate electrode in a plan view (Kim, "active layer 270 may at least partially overlap the gate electrode 220" [Para. 0039, Fig. 2]);
a source area connected to one side of the channel area in the plan view (Kim, "a first active region Al electrically connected to the source electrode 210 [Para. 0039, Fig. 2]); and
a drain area connected to the other side of the channel area in the plan view (Kim, "a second active region A2 electrically connected to the drain electrode 215" [Para. 0039, Fig. 2]), wherein the conductive material layer includes:
a first conductive material layer (Kim, resistive contact layer 271, Fig. 2) on the source area; and
a second conductive material layer on the drain area (Kim, "resistive contact layers 271 and 273 may be interposed between the source electrode 210 and the first active region A1 and between the drain electrode 215 and the second active region A2, respectively" [Para. 0050, Fig. 2]),
wherein the active layer includes an active hole in which the active layer is absent within an area defined by the active layer (Kim, "active layer 270 may include a recess region which is at least partially recessed from one surface of the active layer 270" [Para. 0041, Fig. 3]), and
wherein, in the plan view, the active hole extends from the channel area to the drain area (Kim, "In some embodiments, the entire recess region may be formed to extend in the direction between the first active region A1 and the second active region A2" [Para. 0041, Figs. 6-8]).
Kim does not disclose the first conductive material layer overlaps at least a portion of the channel area.
However, Cho, in the same field of endeavor, teaches a thin film transistor wherein the first conductive material layer (Cho, first conductive layer 141E [Fig. 1E]) overlaps at least a portion of the channel area (Cho, channel region 151E [Fig. 1E]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Cho, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Cho, “to reduce a length of the channel region” [Para. 0050]. This obvious combination is hereinafter referred to as modified Kim.
Regarding claim 2, Kim further discloses a thin film transistor substrate: wherein a portion of the active hole overlaps the gate electrode in the plan view (Kim, "The recess region may include a portion extending in a direction between the first active region A1 and the second active region A2" [Para. 0041, Fig. 3]).
Regarding claim 3, Kim further discloses a thin film transistor substrate: wherein the active hole is spaced apart from the first conductive material layer in the plan view (Kim, Figs. 4-5 illustrate embodiments wherein resistive contact layer 271, which is directly below source electrode 210, is spaced apart from the recess region).
Regarding claim 4, Kim further discloses a thin film transistor substrate: wherein the second conductive material layer is spaced apart from the channel area in the plan view (Kim, "273 may be interposed...between the drain electrode 215 and the second active region A2" [Para. 0050]. This element may be visualized in Figs. 2 & 3 wherein element 273 is directly on top of element A2 (second active region which is analogous to Applicant's drain area) spaced from channel C.).
Regarding claim 5, Kim further discloses a thin film transistor substrate: wherein the source area and the drain area are between the base substrate and the first conductive material layer and the second conductive material layer, respectively (Kim, Fig. 2 shows first active region A1 and second active region A2 (analogous to Applicant's source and drain areas, respectively) in between substrate 50 and elements 271 and 273, respectively), and wherein the first conductive material layer and the second conductive material layer respectively contact the active layer (Kim, "the resistive contact layers 271 and 273 may be interposed between the source electrode 210 and the first active region A1 and between the drain electrode 215 and the second active region A2, respectively" [Para. 0050]).
Regarding claim 6, Kim further discloses a thin film transistor substrate: further comprising a source electrode and a drain electrode spaced apart from each other and respectively contacting the source area and the drain area, and (Kim, "source electrode 210 and the drain electrode 215 may be spaced apart from each other to face each other, and may be electrically connected to the active layer 270 through first and second contact holes 211 and 213 formed in the gate insulating film 240 and the interlayer insulating film 245" [Para. 0037]) wherein the gate electrode, the source electrode, and the drain electrode are on the same layer (Kim, "the interlayer insulating film 245 may be formed between the gate electrode 220 and the source and drain electrodes 210 and 215, thereby insulating them from each other" [Paras. 0033-0035]).
Regarding claim 7, Kim further discloses a thin film transistor substrate: wherein the active hole has a plurality of sub-active holes (Kim, "through holes 315 and 335 may include two or more sub-through holes 310, 320 and sub-through holes 330 and 340" [Para. 0059]), wherein the plurality of sub-active holes is spaced apart from each other (Kim, "each through hole may be partially blocked such that four sub-through holes 310, 320, 330 and 340 are formed in the active layer 300" [Para. 0059]), and wherein each of the plurality of sub-active holes have an elongated shape extends from the channel area to the drain area (Kim, "sub-through holes 310, 320 and sub-through holes 330 and 340, respectively, extending in a line, e.g. in rows, from the source electrode 210 to the drain electrode 215" [Para. 0059, Figs. 5-7]).
Regarding claim 8, Cho further discloses a thin film transistor substrate: wherein the conductive material layer includes at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO) (Cho, "conductive layer 140A may be made from the same material as that of the gate electrode 120A" [Para. 0027] wherein “the gate electrode 120A may be multiple layers made from any one selected from a group consisting of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or an alloy thereof” [Para. 0035]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to form the conductive material layer of Kim, as modified by Cho, from at least one of from titanium, molybdenum, aluminum, silver, copper, chromium, or neodymium, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. Cho expressly teaches this same closed list of metals as suitable materials for the auxiliary electrode already incorporated into the combination and Kim independently teaches substantially the same list of metals as suitable materials for conductive electrodes within the identical thin film transistor substrate. The correspondence between the metal lists disclosed in two independent references directed to conductive electrodes in thin film transistor substrates evidences that this is a known, finite genus of interchangeable materials recognized in the art, rather than an unexpected selection. Selection of any member of this known genus for the conductive material layer amounts to nothing more than a simple substitution of one known element for another to obtain predictable results, or a choice from among a finite number of identified solutions, with a reasonable expectation that the selected material would perform its intended function of providing electrical conductivity for the conductive material layer.
Regarding claim 19, Cho further discloses a thin film transistor substrate: wherein the active layer includes an oxide semiconductor material, and wherein the oxide semiconductor material includes at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials (Cho, "examples of a constituent material of the oxide semiconductor includes…a ternary metal oxide such as an indium—gallium—zinc—oxide (In—Ga—Zn—O)-based material" [Para. 0028]).
Regarding claim 20, Cho further discloses a display apparatus comprising the thin film transistor substrate of claim 1 (Cho, “the thin-film transistors according to various exemplary embodiments of the present invention are applied to the driving transistor TR2 of the display device 300” [Para. 0075]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over modified Kim as applied to claim 1 above, and further in view of Yamazaki US 2014/0103346 A1 (hereinafter Yamazaki).
Regarding claim 9, Yamazaki discloses a transistor substrate: wherein a shortest distance from the drain area to the first conductive material layer is a first length (Yamazaki, "a distance between the conductive layer 406a and the conductive layer 406b…called channel length L” [Para. 0047, Fig. 1A]), wherein a shortest length in a channel length direction of the active layer that the first conductive material layer overlaps the gate electrode in the plan view is a second length (Yamazaki, “a length in the channel length L direction (denoted by Lov in FIG. 1A) of a region in the stacked-layer oxide film 414 where the gate electrode 418 overlaps with…the conductive layer 406a or the conductive layer 406b” [Para. 0065, Fig. 1A]), and wherein the first length is longer than the second length (Yamazaki, "Lov is higher than 0% and less than 20% of the channel length L, preferably greater than or equal to 5% and less than 10% of the channel length" [Para. 0065]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kim with the teachings of Yamazaki, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so is expressly recognized by Yamazaki because “[w]ith such a structure, parasitic capacitance generated between the gate electrode 418 and the drain electrode 416b can be small” [Para. 0065].
Claims 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over modified Kim as applied to claim 1 above, and further in view of Jang et al. US 2022/0208804 A1 (hereinafter Jang).
Regarding claim 11, Jang discloses a transistor substrate further comprising: a light blocking layer on the substrate (Jang, "a light shielding layer is provided on an upper surface of a substrate 111" [Para. 0064]); and a storage capacitor in an overlapping area between the light blocking layer and the thin film transistor (Jang, "a first light shielding capacitor electrode 112b extended from the light shielding electrode 112a and overlapped with the first active capacitor electrode 115a" [Para. 0087, Fig. 6B]. Refer to Cst1_2 in Fig. 6B which overlaps light shielding layer 112, buffer 113, and active layer 114).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Kim with the teachings of Jang, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. Modified Kim discloses the thin film transistor substrate of claim 1, and Kim further discloses that “since the through holes 250 and 255 may be formed in the active layer 270, it is possible to further reduce the leakage current by reducing an absolute space in which the leakage current can flow. By reducing the leakage current, the size of a storage capacitor 150 that will be described later may be reduced, thereby improving an opening ratio” [Para. 0045]. Kim expressly identifies storage capacitor size and aperture ratio as a design consideration of the claim 1 substrate. Jang addresses this same consideration: “when the size of the conductor provided in the pixel is increased, a size of an opening through which light generated from the light emitting element provided in the pixel is emitted to the outside is reduced” [Para. 0006] and further provides a solution of “a storage capacitor including at least three electrodes to reduce a size of the driving transistor or the storage capacitor” [Abstract], formed by reusing the light shielding electrode, active-layer electrode, and gate electrode already present in the transistor substrate as capacitor plates. As such, Jang notes that “the storage capacitor Cst applied to the present disclosure may form the same or similar capacitance as or to that of the conventional capacitor at a size smaller than that of the conventional capacitor” and, therefore, “a size of an opening may be increased as much as a reduced size of the storage capacitor” [Para. 0099]. One skilled in the art would have thus been motivated to incorporate Jang’s storage capacitor architecture since doing so applies a known technique to a device already identified as amenable to such optimization, with a reasonable expectation of success.
Regarding claim 12, Jang further discloses a transistor substrate: wherein the storage capacitor includes a first storage capacitor (Jang, capacitor Cst1_2), the first storage capacitor including: a first capacitor electrode connected to the light blocking layer (Jang, "a first light shielding capacitor electrode 112b extended from the light shielding electrode 112a and overlapped with the first active capacitor electrode 115a" [Para. 0087]); and a second capacitor electrode connected to the active layer (Jang, "first electrode 114a of the driving transistor Tdr and the first active capacitor electrode 115a are integrally formed" [Para. 0088]), and wherein the first capacitor electrode and the second capacitor electrode are spaced apart from each other and overlap each other to form a first capacitor (Jang, "storage capacitor Cst also includes a (1-2)th capacitor Cst1_2 comprised of the first active capacitor electrode 115a and a first light shielding capacitor electrode 112b that extends from the light shielding electrode 112a to overlap with the first active capacitor electrode 115a" [Para. 0095]).
Regarding claim 13, Jang further discloses a transistor substrate: wherein the first storage capacitor includes a third capacitor electrode connected to the gate electrode (Jang, "storage capacitor Cst includes a (1-1)th capacitor Cst1_1 comprised of a first active capacitor electrode 115a and a first gate capacitor electrode 118b" [Para. 0095]), and wherein the second capacitor electrode and the third capacitor electrode are spaced apart from each other and overlap each other to form a second capacitor (Jang, "gate capacitor electrode 118b that extends from the gate electrode 118a of the driving transistor Tdr to overlap with the first active capacitor electrode 115" [Para. 0095]).
Regarding claim 14, Jang further discloses a transistor substrate wherein the second capacitor electrode includes: a first layer integrated with any one of the source area and the drain area (Jang, "first active capacitor electrode 115a includes a first reference electrode 115a1 extended from the semiconductor portion 114c of the active portion 114" [Para. 0090]); and a second layer integrated with any one of the first conductive material layer and the second conductive material layer (Jang, "second reference electrode 115a2 may be formed of a metal material. For example, the second reference electrode 115a2 may be an alloy (MoTi) comprised of molybdenum and titanium" [Para. 0092]).
Regarding claim 15, Jang further discloses a transistor substrate: wherein the second capacitor electrode is between the first capacitor electrode and the third capacitor electrode (Jang, Fig. 6B illustrates the common electrode 115a for Cst1_1 and Cst1_2 which lies in between the end connections for the respective storage capacitors), and wherein the third capacitor electrode is connected to the first capacitor electrode (Jang, "first gate capacitor electrode 118b and the first light shielding capacitor electrode 112b are connected to each other through the second contact hole CH2" [Para. 0093]).
Regarding claim 16, Jang further discloses a transistor substrate: wherein the storage capacitor includes a second storage capacitor formed by separating and overlapping the gate electrode and the first conductive material layer (Jang, "first gate capacitor electrode 118b extended from the gate electrode 118a and overlapped with the first active capacitor electrode 115a" [Para. 0087] wherein "115a includes...a second reference electrode 115a2" [Para. 0090] comprised of conductive material).
Regarding claim 17, Jang further discloses a transistor substrate: wherein the storage capacitor includes a third storage capacitor formed by separating and overlapping the gate electrode and the light blocking layer from each other (Jang, "an electrode of the storage capacitor is connected to at least one of the light shielding electrode and the gate electrode" [Clm. 1]).
Regarding claim 18, modified Kim in further view of Jang discloses the thin film transistor substrate of claim 17.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to position the third storage capacitor of modified Kim and Jang in an area overlapping the active hole in order to reduce the conductive footprint within the pixel and thereby increase the opening ratio. The active hole region, wherein the active layer is absent, cannot be used for active-layer-based structures. Furthermore, vertically arranging the capacitor plates as described in claim 17 within the recessed region, rather than occupying separate lateral area elsewhere in the pixel, would reduce the total area occupied by conductive structures. Such a modification would have had a reasonable expectation of success because it requires no additional fabrication step, mask, or material beyond those already taught by the references.
This modification is motivated by the express teachings of Kim and Jang, which recognize that reducing the area occupied by storage capacitors and other conductive structures increases the available pixel opening. Kim discloses that “since the through holes 250 and 255 may be formed in the active layer 270, it is possible to further reduce the leakage current by reducing an absolute space in which the leakage current can flow. By reducing the leakage current, the size of a storage capacitor 150 that will be described later may be reduced, thereby improving an opening ratio” [Para. 0045]. Jang discloses that “when the size of the conductor provided in the pixel is increased, a size of an opening through which light generated from the light emitting element provided in the pixel is emitted to the outside is reduced” [Para. 0006]. Furthermore, Jang teaches that “the storage capacitor Cst applied to the present disclosure may form the same or similar capacitance as or to that of the conventional capacitor at a size smaller than that of the conventional capacitor. Therefore, a size of an opening may be increased as much as a reduced size of the storage capacitor” [Para. 0099].
Allowable Subject Matter
Claim 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, modified Kim anticipates the thin film substrate of claim 1 wherein a portion of the active hole overlaps the gate electrode and wherein a shortest length in a channel length direction of the active layer that the active hole overlaps the gate electrode is a third length. Prior art does not disclose a shortest distance from the active hole to the first conductive material layer in the channel length direction of the active layer is a fourth length and that the fourth length is longer than the third length.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GERALD H BISSELL whose telephone number is (571) 272-0834. The examiner can normally be reached Mon - Fri 0800 - 1600.
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/GERALD H. BISSELL/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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