DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 08/20/2026 Amendment.
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,665,628 to Kawashima (hereafter Kawashima) in view of US 10,950,279 to Jeong (hereafter Jeong).
Regarding independent claim 1, Kawashima teaches a memory device, comprising:
a plate line (FIG. 1: PL0);
a pair of ferroelectric layers implementing a pair of memory cells of a plurality of memory cells arranged along the plate line and coupled to opposite sides of the plate line, wherein the plate line is disposed between the pair of ferroelectric layers such that each ferroelectric layer of the pair of ferroelectric layers is adjacent to and coupled to a respective opposite side of the plate line, the pair of ferroelectric layers being across the plate line from each other (FIG. 1: e.g. ferroelectric capacitors C00 and xC00 couple along the plate lines PL0 on opposite sides);
a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers (FIG. 1: bit lines BL0 and xBL0 coupled to ferroelectric capacitors C00 and xC00 via access gates Q00 and xQ00, respectively); and
a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the pair of digit lines from the respective memory cells (FIG. 14: latch amplifier LA0), wherein the sense amplifier comprises:
Kawashima does not teach the strike through limitations.
Jeong teaches a memory device comprising a sense amplifier coupled to a pair of digit lines (see FIG. 2A), wherein the sense amplifier comprises:
a pair of inverters configured to selectively couple to the pair of digit lines (FIG. 2A: inverters 220 and 210 coupled to BLT and BLB via isolation transistors 251 and 252, respectively); and
a pair of switches (FIG. 2A: transistors 241 and 242) each configured to cause a respective inverter of the pair of inverters to function as a unity gain amplifier during a compensation phase of the memory device (during offset cancelation operation 320 of FIG. 3, BLSA circuit 200 functions as unity gain amplifier as in FIG. 4).
Since Kawashima and Jeong are both from the same field of endeavor, the purpose disclosed by Jeong would have been recognized in the pertinent art of Kawashima.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to employ the BLSA of Jeong as the sense amplifier of Kawashima for more accurate amplification and sensing operation (see 2:4-28).
Regarding dependent claim 2, Jeong teaches wherein the pair of inverters comprises: a first complementary metal-oxide semiconductor inverter; and a second complementary metal-oxide semiconductor inverter (FIG. 2A: see inverters 220 and 210).
Regarding dependent claim 3, Jeong teaches wherein each of the pair of switches is configured to connect an input of a respective inverter of the pair of inverters to a corresponding output of the respective inverter of the pair of inverters as a feedback connection (see FIG. 4).
Regarding dependent claim 4, Jeong teaches wherein the memory device comprises a voltage source; and a voltage switch that is configured to couple source terminals of p-channel transistors of the pair of inverters to the voltage source (transistor 291 of FIG. 2C coupling VDD to node RTO of FIG. 2A, wherein transistor 291 in response to signal SAP1) during threshold compensation using the compensation phase (FIG. 3: signal SAP1 is active high during offset cancelation operation 320).
Jeong teaches a voltage source instead of a current source. However, it would have been obvious to replace current source with a voltage source because they are interchangeable with respect to supplying power to electronic parts.
Regarding dependent claim 5, Jeong teaches wherein the compensation phase is configured to cause the pair of inverters to amplify input values similarly to each other (FIG. 2C shows nodes RTO and SB being equalized to the same value for each of the inverter; FIG. 4 shows the pair of inverters have similar connection for unity gain amplifiers).
Regarding dependent claim 6, Jeong teaches wherein the compensation phase is configured to settle input and output voltages of the pair of inverters to enhance gains of the pair of inverters (see FIG. 4).
Regarding dependent claim 7, Jeong teaches wherein the gains are negative gains (FIG. 4: because the feedback from output to input of inverter has opposite value).
Regarding dependent claim 8, Jeong implicitly teaches wherein the gains of the pair of the inverters are optimized at respective locations on respective characteristic-dependent output response curves (FIG. 4: because unity gain amplifiers corresponding to each of the inverters are independent from each other and each unity amplifier responses to voltage on the corresponding bit line during compensation phase) corresponding to a greatest gain of the respective characteristic-dependent output response curves (FIG. 2C: the greatest gain due to voltages on both inverters have been equalized, in addition to charge compensating before sensing and amplifying the voltage difference between pair of bit lines).
Regarding dependent claim 9, Jeong teaches wherein the memory device comprises an isolation pair of switches to couple gut nodes of the sense amplifier to respective digit lines of the pair of digit lines during the compensation phase (FIG. 2A: transistors 251 and 252).
Regarding dependent claim 10, Jeong teaches wherein the compensation phase comprises charging respective digit lines of the pair of digit lines with values specific to characteristics of respective inverters of the pair of inverters (see FIG. 2A and precharge phase 310 of FIG. 3 with signals EQ and ISO active high).
Regarding independent claim 11, Kawashima teaches a memory device, comprising
a plurality of ferroelectric layer-based memory cells to store data (see FIG. 1);
a plurality of plate lines (FIG. 1: PL0 to PLn), wherein each plate line of the plurality of plate lines is disposed between a first ferroelectric layer of a respective ferroelectric layer-based memory cell of a first set of the plurality of ferroelectric layer-based memory cells and a second ferroelectric layer of a respective ferroelectric layer-based memory cell of a second set of the plurality of ferroelectric layer-based memory cells, such that the first ferroelectric layer and the second ferroelectric layer are adjacent to and coupled to opposite sides of the plate line and are disposed across the plate line from each other, and a plurality of the ferroelectric layer-based memory cells are arranged along each plate line of the plurality of plate lines (FIG. 1: e.g. ferroelectric capacitors C00-C0m and xC00-xC0m couple along the plate lines PL0 on opposite sides);
a plurality of first digit lines each coupled to a respective ferroelectric layer-based memory cell of a first set of the plurality of ferroelectric layer-based memory cells (FIG. 1: e.g. bit line BL0 coupled to ferroelectric capacitor C00 via access gates Q00);
a plurality of second digit lines each coupled to a respective ferroelectric layer-based memory cell of a second set of the plurality of ferroelectric layer-based memory cells (FIG. 1: e.g. bit line xBL0 coupled to ferroelectric capacitor xC00 via access gates xQ00); and
a plurality of sense amplifiers (FIG. 14: latch amplifier LA0 to LA1) each respectively coupled to a first digit line from the plurality of first digit lines and to a second digit line from the plurality of second digit lines,
Kawashima does not teach the strike through limitations.
Jeong teaches a memory device comprising a sense amplifier coupled to a pair of digit lines (see FIG. 2A), wherein the sense amplifier comprises: a pair of inverters configured to selectively couple to the first and second digit lines (FIG. 2A: inverters 220 and 210 coupled to BLT and BLB via isolation transistors 251 and 252, respectively), and each inverter of the pair of inverters comprises a switch (FIG. 2A: transistors 241 and 242) configured to cause the respective inverter to function as a unity gain amplifier during a compensation phase of the memory device (during offset cancelation operation 320 of FIG. 3, BLSA circuit 200 functions as unity gain amplifier as in FIG. 4).
Since Kawashima and Jeong are both from the same field of endeavor, the purpose disclosed by Jeong would have been recognized in the pertinent art of Kawashima.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to employ the BLSA of Jeong as the sense amplifier of Kawashima for more accurate amplification and sensing operation (see 2:4-28).
Regarding dependent claim 12, Kawashima teaches wherein each of the sense amplifiers of the plurality of sense amplifiers is configured to sense and amplify a voltage difference between voltages on the respective first and second digit lines (FIG. 2: because sense amplifier SA is a differential amplifier).
Regarding dependent claim 13, Kawashima wherein each of the first set of the plurality of ferroelectric layer-based memory cells is configured to store data, and each of the second set of the plurality of ferroelectric layer-based memory cells is configured to store complementary data (FIG. 2: memory cells 90 and ’90 store complementary data).
Regarding dependent claim 14, Kawashima teaches wherein the first digit lines are configured to carry the data (FIG. 2: because bit line BL is true bit line for carrying true data).
Regarding dependent claim 15, Kawashima teaches wherein the second digit lines are configured to carry a complement of the data (FIG. 2: because bit line BLB is complementary bit line for carrying complement data).
Regarding dependent claim 16, Jeong teaches a voltage source that selectively supplies a voltage to the pair of inverters (transistor 291 of FIG. 2C coupling VDD to node RTO of FIG. 2A, wherein transistor 291 in response to signal SAP1).
Jeong teaches a voltage source instead of a current source. However, it would have been obvious to replace current source with a voltage source because they are interchangeable with respect to supplying power to electronic parts.
Regarding dependent claim 17, Jeong teaches wherein each of the switches is configured to couple together an input and an output of the respective inverter during the compensation phase before one or more amplification phases of the respective sense amplifier (during offset cancelation operation 320 of FIG. 3, signal OC turns on transistors 241 and 242 of FIG. 2A, and the input and output of respective inverter coupled together as in FIG. 4).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,950,279 to Jeong (hereafter Jeong) in view of US 7,505,341 to Kim et al. (hereafter Kim).
Regarding independent claim 18, Jeong teaches a method, comprising:
toggling a first switch in a sense amplifier (FIG. 2A: turning on switch 241 with signal OC active high in FIG. 3) during a compensation phase (FIG. 3: during compensation phase 320) to couple a first input of a first inverter to a first output of the first inverter to cause the first inverter of the sense amplifier to be configured as a unity gain amplifier during the compensation phase of the sense amplifier (FIG. 4: see connection of inverter 210) to cause amplification in the first inverter to be enhanced in subsequent amplification phases of the sense amplifier by storing a first charge on a first digit line of the sense amplifier (FIG. 4: charge on BLT);
toggling a second switch in the sense amplifier (FIG. 2A: turning on switch 242 with signal OC active high in FIG. 3) during the compensation phase (FIG. 3: during compensation phase 320) to couple a second input of a second inverter to a second output of the second inverter (FIG. 4: see connection of inverter 220) to cause the second inverter of the sense amplifier to be configured as a unity gain amplifier during the compensation phase of the sense amplifier to cause amplification in the second inverter to be enhanced in the subsequent amplification phases of the sense amplifier by storing a second charge on a second digit line of the sense amplifier (FIG. 4: charge on BLB);
;
in an amplification phase (FIG. 3: during amplification operation 340), disconnecting the first input from the first output (FIG. 2A: turning off switch 241 with signal OC active low in FIG. 3);
in the amplification phase, disconnecting the second input from the second output (FIG. 2A: turning off switch 242 with signal OC active low in FIG. 3); and
amplifying a signal difference from memory cells corresponding to the sense amplifier by using the enhanced amplification in the first and second inverters (with voltages on both inverters have been equalized and charge compensating beforehand, the amplification on voltage difference between pair of bit lines is enhanced).
Jeong does not teach the strike through limitations.
Kim teaches a method for operating a differential amplifier, wherein the differential amplifier comprises cross-coupled inverters (FIG. 3: first inverter comprising transistors 20 and 24, and second inverter comprising transistors 22 and 26) selectively coupling to a pair of digit lines (FIG. 3: digit lines D and D_). The method further comprises selectively coupling terminals of n-channel transistors of the first and second inverters to a negative voltage that is less than 0 volts (FIGS. 3 and 4A: selectively coupling transistors 24 and 26 to -0.3V using N-latch driver circuit 60).
Since Jeong and Kim are both from the same field of endeavor, the purpose disclosed by Kim would have been recognized in the pertinent art of Jeong.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the voltage scheme suggested in Kim to the sense amplifier of Jeong in order to quickly and reliably sense data stored in memory cells while the semiconductor memory of Jeong operates at a reduced supply voltage (see 2:42-45).
Regarding dependent claims 19-20, Jeong teaches applying a deflection voltage to reduce voltages in the first and second digit lines during a voltage level development between the compensation phase and the subsequent amplification phases via capacitors coupled to the first and second digit lines (FIG. 2A: via capacitors 231 and 232).
Response to Arguments
Applicant’s arguments, filed 08/20/2026, with respect to the rejections of claims 1, 11, 18 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly discovered references to Kawashima and Kim as stated above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 7, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
