Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 02/14/2022. It is noted, however, that applicant has not filed a certified copy of the JP2022-020862 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 5-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 3 recites the limitation “the second terminal of the voltage limiting transistor” in lines 17-18. There is insufficient antecedent basis for this limitation in the claim.
Regarding claims 5-15 are rejected due to their dependency on the rejected claim 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20160118941 A1) in view of Koizumi et al.(US 7990221 B2), hereafter referred to as “Wang” and “Koizumi”, respectfully.
Regarding claim 1, in the embodiment of Figs. 1-3, Wang discloses:
A limiter circuit (Figs. 1-3, pre-processing circuitry 10 (i.e. RF envelope detection module 826 shown in Figs. 9-11, 10A-10D) and envelope signal amplification circuitry 111/11 form a limiter circuit) connected to an amplifying transistor (radio frequency power amplifier 12 (comprising RF transistor 120)) that amplifies and outputs a radio frequency signal (input radio frequency signal RF_in (output from digital upconverter 800 shown in Fig. 9-11) and outputs amplified radio frequency signal RF_amp in Figs. 1-3), the limiter circuit being configured to control a voltage applied to the amplifying transistor based on the radio frequency signal (voltage level of the power supply of the power amplifier is controlled in relation to the envelope of the RF signal per paragraph [0003] lines 7-15, thereby the transistor 110 (of envelope signal amplification circuitry 11) amplifies the input envelope signal to produce the amplified envelope signal and used as the supply voltage for the RF power amplifier 12, per paragraph [0039] lines 1-4),
the limiter circuit comprising:
an input signal detection (RF envelope detection module 826 shown in Figs. 10A-10D) configured to detect a power of the radio frequency signal (RF envelope detection module 826 which detects the envelope of the signal and outputs the pre-input envelope signal, per paragraph [0078] lines 5-8); and
a voltage limiting transistor (transistor 110 of envelope signal amplification circuitry 11) configured to limit the voltage applied to the amplifying transistor based on a current flowing to the input signal detection transistor (current flowing between the source/collector and the emitter/drain terminals is modulated based on the input envelope signal, per paragraph [0037], the input envelope signal is based on the pre-input envelope signal (paragraph [0094]) that is produced by the RF envelope detection module 826 per paragraph [0078] lines 5-8).
Regarding claims 2, 16, and 17 in the embodiment of Figs. 1-3, Wang discloses:
A limiter circuit (Figs. 1-3, pre-processing circuitry 10 (i.e. RF envelope detection module 826 shown in Figs. 9-11, 10A-10D) and envelope signal amplification circuitry 111/11 form a limiter circuit) comprising:
an input terminal (baseband I and Q data signal inputs shown in Figs. 1-3 and 8-11);
an output terminal (amplified radio frequency signal output at RF_amp);
an input signal detection (RF envelope detection module 826 shown in Figs. 10A-10D) that is electrically connected to the input terminal (826 is connected along the envelope path via digital upconverter 800) and that is configured to detect a power of a radio frequency signal (RF envelope detection module 826 which detects the envelope of the signal and outputs the pre-input envelope signal, per paragraph [0078] lines 5-8); and
a voltage limiting transistor (transistor 110 of envelope signal amplification circuitry 11) having a first terminal (110 source, note: the terminals of transistor are described in paragraph [0037]-[0038]) that is electrically connected to the output terminal (via inductor 17-1), and a third terminal (110 drain terminal) electrically connected to a first supply voltage terminal (voltage source 14 provides voltage V_bat and is applied to the drain terminal of 110, per paragraph [0038]),
wherein an amplifying transistor (radio frequency power amplifier 12) that is between the input terminal and the output terminal (amplifier 12 is connected between I and Q data input and RF_amp, as shown in Figs. 1-3) configured to amplify and output a radio frequency signal (input RF signal RF_in to amplified radio frequency signal RF_amp, per claims 16 and 17) is connected between the input terminal and the output terminal (amplifier 12 is connected between I and Q data input and RF_amp, as shown in Figs. 1-3).
However, Wang is silent in teaching the input signal detection uses a transistor and a plurality of amplifier circuits, wherein at least one of the plurality of amplifier circuits other than a final stage amplifier circuit comprises the limiter circuit.
Koizumi teaches:
An input signal detection transistor (Figs. 5 and 6, shown Detector circuit 10 comprising of transistors 29/23) and a plurality of amplifier circuits (Figs. 8-11, driver stage amplification circuit 33 and final stage amplification circuit 34).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have replaced the generic signal detector as taught by Wang (Figs. 8-11) with the detector circuit as taught by Koizumi (Figs. 5 and 6) to detects the inputting power (per column 2 lines 1-2 and in the ABSTRACT lines 1-5), thereby suggesting the obviousness of such a combination. Furthermore, it would be obvious for the amplifier circuits comprising the limiter circuit taught in Wang (Fig. 1) to be a plurality of amplifier circuits as taught in Koizumi (Figs. 8-11) to cause a difference in the distortion characteristics in each stage (column 2, lines 14-16), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 3 and 5-15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 3, 4, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3, 4, and 18:
the cited prior art of record, either singly or in proper combination, Wang (US 20160118941 A1), does not teach or make obvious, along with the other claimed features,
the “choke inductor is connected between the third terminal of the voltage limiting transistor and the first supply voltage terminal,” and “a second coupling capacitor is connected between a second terminal of the input signal detection transistor and the input terminal” per claims 3 and 4, and
the “second bias resistor is connected between the second terminal and a second bias voltage terminal”, per claim 18.
Claims 5-15 are also objected to as being dependent on claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
