Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments, filed on 02/06/2026, are acknowledged. Amended claims 1-4, 12, 15,19 and cancelled claim 13 are acknowledged.
Response to Arguments
3. Applicant’s arguments, see pg. 9, with respect to the rejection of claim
1 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the
rejection has been withdrawn.
However, upon further consideration, a new ground of rejection is made in view of
“Sony” ( Sony Develops World's First*1Stacked CMOS Image Sensor Technology with 2-Layer Transistor Pixel).
4. The amended subject matter in claim 1 reads:
“…wherein in a plan view perpendicular to the third direction of the image sensor, the pre-charge transistor of the second semiconductor chip overlaps with two or more of the plurality of pixel regions of the first semiconductor chip…”.
In the “Non-Final Rejection”, dated 11/12/2025, in claim 1, the limitation “a plurality of pixel regions” is mapped with respect to Lee, corresponding to a pixel array 110. Lee is referenced as teaching a first semiconductor chip including the plurality of pixel regions (pixel array). Lee is also referenced as teaching “…wherein the plurality of pixel regions share the pre-charger transistor…”. Further, Lee is referenced as teaching the image sensor and a corresponding digital signal processor (DSP) being implemented as individual chips. However, Lee doesn’t specify additional examples of implementing these individual chips, as is further limited in newly amended claim 1.
However, Sony teaches a stacked CMOS image sensor of a layered transistor pixel. Pg. 2 lines 6-15 teaches a technology which separates the photodiodes and pixel transistors on different substrate layers.
As noted above, Lee is referenced as teaching a shared transistor between a first and second pixel. Sony teaches photodiodes and pixel transistors on different substrates stacked “atop the other”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a shared transistor between two pixels, as taught by Lee, can be implemented through the technology as taught by Sony, wherein photodiodes and transistors are formed on different substrates which are layered atop one another (thus a pixel region of a substrate is in an overlapping relationship with a secondary transistor layer); thus giving an image sensor more dynamic range by increasing saturation signal level.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al.
(US 2022/0094864 A1) in view of Sony (Sony Develops World's First*1Stacked CMOS Image Sensor Technology with 2-Layer Transistor Pixel).
7. Regarding claim 1, an image sensor (…Lee teaches an image sensor 100 in [0023];
Fig. 1…) comprising:
a first semiconductor chip which extends in first and second directions that intersect
each other (…Lee, in [0023], teaches the image sensor (which extends in intersecting
vertical and horizontal directions of Fig. 1) and a corresponding DSP which may be
implemented as individual chips…), and
includes a pixel part comprising a plurality of pixel regions (…Lee, in [0024], teaches
pixel array 110; which may be viewed as having a plurality of regions; Fig. 1…); and
a second semiconductor chip comprising a circuit part connected to the pixel
part, on the first semiconductor chip (…Lee, in [0023], teaches the image sensor and a
corresponding DSP may be implemented as individual chips…), wherein
the pixel part of the first semiconductor chip comprises:
a photodiode (…wherein [0039] teaches photodiode PD; Fig. 3…),
a floating diffusion node which accumulates photocharges generated by the photodiode
(…wherein [0042] teaches floating diffusion node FD; Fig. 3…), and
a first source follower which amplifies and outputs a signal corresponding to a change in
potential of the floating diffusion node (…wherein [0044] teaches source follower SF1 which
buffers and amplifies a signal according the potential of FD…), wherein
the circuit part of the second semiconductor chip comprises:
a first pre-charge selection transistor connected between a first node and a second node
(…wherein [0041] teaches PSX1, as a first precharge select transistor connected between
ND1 and ND2; Fig. 3…),
a second pre-charge selection transistor connected to the first pre-charge selection
transistor (…[0042] teaches PSX2, as a second precharge select transistor connected to
PSX1, as depicted in Fig. 3…), and
a pre-charge transistor to pre-charge the second node connected to the first source
follower (…wherein [0041 teaches a precharge transistor PCX; which precharges node
NO2 (which is connected to source follower SF1; Fig. 3…).
Lee doesn’t further specify wherein
in a plan view perpendicular to the third direction of the image sensor, the precharge transistor of the second semiconductor chip overlaps with two or more of the plurality of pixel regions of the first semiconductor chip (…wherein Lee is referenced as teaching a shared transistor between a first and second pixel. Sony further teaches photodiodes and pixel transistors on different substrates stacked “atop the other”.
Additionally, a first and second semiconductor chip, in view of Lee and Sony, in a broad interpretation, can yield different design of circuits which posses the same electronic components
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a shared transistor between two pixels, as taught by Lee, can be implemented through the technology as taught by Sony, wherein photodiodes and transistors are formed on different substrates which are layered atop one another (thus a pixel region of a substrate is in an overlapping relationship with a secondary transistor layer); thus giving an image sensor more dynamic range by increasing saturation signal level….).
8. Regarding claim 2, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above),wherein
in the plan view the pre-charge transistor extends in the first direction over the plurality of pixel regions adjacent to each other in the first direction (…as depicted in Fig. 1, pixel array 110 extends in the vertical and horizontal direction and [0129] teaches that the precharge transistor PCX may be shared between a first and a second pixel; as such it may be viewed that such a shared component could extend in a first or second direction over a plurality of pixels so to be shared; from the viewpoint of Fig. 1...).
9. Regarding claim 3, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above), further comprising
a plurality of pre-charge transistors spaced apart from each other in the second direction in the plan view to include the pre-charge transistor (…wherein [0129] teaches that the
precharge transistor PCX may be shared between a first and a second pixel; a plurality of
such a shared component would have to be arranged in a manner which would
accommodate the pixel array 110 and the multitude of pixels thereof in either a first or
second direction, so to provide each pair of pixels of the array the shared transistor…).
10. Regarding claim 4, Lee in view of Sony teaches the image sensor of claim 3 (see claim 3 above), wherein first and second active regions in which the plurality of pre-charge transistors are each disposed are spaced apart from each other in the second direction, in the plan view (…wherein [0129] teaches that the precharge transistor PCX (containing active regions) may be shared between a first and a second pixel; a plurality of such a shared component would have to be arranged in a manner which would
accommodate the pixel array 110 and the multitude of pixels thereof in either a first or
second direction, so to provide each pair of pixels of the array the shared transistor…).
11. Regarding claim 5, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above), wherein
the first pre-charge selection transistor and the second pre-charge selection transistor
connected to the pre-charge transistor are disposed in different pixel regions from each other
(…wherein PSX1 and PSX2 of a pixel may correspond to share a PCX with another pixel,
the PCX could be disposed in a region that is common to both pixels, never the less also
be not in the same region…).
12. Regarding claim 6, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above), wherein
the circuit part further comprises
a second source follower that amplifies and outputs a signal corresponding to a change
in potential of the first node (…wherein [0054] teaches source follower SF2 which amplifies
a potential change of output node NO1; Fig. 3…), and
an extension length of the pre-charge transistor is longer than an extension length of the
second source follower, on the basis of the first direction (…on the basis that Lee teaches that the precharge transistor PCX may be shared between a first and a second pixel (as
taught in [0129]), it may be broadly reasoned that the shared PCX would extend to a
greater length in order to be shared between pixels ( in either direction of pixel
arrangement and circuit sharing) and thus have a longer extension than SF2 which is not
a shared component a pixel’s circuitry…).
13. Regarding claim 7, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above), wherein
the circuit part further comprises:
a first capacitor connected to the first node (…wherein [0041] teaches C1 connected
to NO1 through SAMP1; Fig. 3…), and
a first sampling transistor that samples electric charges to the first capacitor (…wherein
[0050] teaches sampling transistor SAMP1 connected to C1; Fig. 3…); and
a second capacitor connected to the first node (…wherein [0052] teaches C2
connected to NO1 through SAMP2; Fig. 3…), and
a second sampling transistor that samples electric charges to the second capacitor
(…wherein [0052] teaches sampling transistor SAMP2 connected to C2…).
14. Regarding claim 8, Lee in view of Sony teaches the image sensor of claim 7 (see claim 7 above), wherein
the first capacitor stores electric charges according to a voltage of the floating diffusion
node being reset (…wherein [0051] teaches that charges from a reset operation of node
FD may be stored in capacitor C1…), and
the second capacitor stores electric charges according to the voltage of the floating
diffusion node in which the photocharges are accumulated (…wherein [0053] teaches that
charges of photocharge accumulation in the floating diffusion node FD may be stored in
the second capacitor C2…).
15. Regarding claim 9, Lee in view of Sony teaches the image sensor of claim 7 (see claim 7 above), wherein
the circuit part further comprises:
a third capacitor connected to the first node (…wherein Lee, in accordance with Fig.
17, teaches C3 which is connected to a node NO2 (a corresponding node of NO1 of Fig.
3)…), and a third sampling transistor that samples electric charges to the third capacitor
(…wherein [0143] teaches sampling transistor SAMP3 connected to C3; Fig. 17…).
16. Claims 10-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al.
(US 2022/0094864 A1) in view of Sony (Sony Develops World's First*1Stacked CMOS Image Sensor Technology with 2-Layer Transistor Pixel) and further view of Moradi Khanshan et al. (US 2024/0137668 A1; further referred to as Moradi).
17. Regarding claim 10, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above).
Though Lee, in [0023], teaches that the image sensor and a corresponding DSP
may be implemented as individual chips; Lee does not further teach the image sensor of
claim 1 comprising:
a bonding structure which bonds a first bonding metal of a bottom of the first
semiconductor chip and a second bonding metal of a top of the second semiconductor chip
(…however, Moradi, in [0142] teaches electrical connection between a pixel substrate 100
and a logic substrate 200 performed through TCVs (wherein it is well -known in the art to
use metal conductors as such copper pads to bond) between a pad region and a c circuit
region.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that through chip via technology as taught
by Moradi could have been implemented in the teaching of Lee, so to create common
connection points between shared components of different pixels yet also isolate the
pixel component providing more pixel area on a substrate…).
18. Regarding claim 11, Lee in view of Sony teaches the image sensor of claim 1 (see claim 1 above),
further comprising:
a transfer transistor (…wherein Lee, in [0042], teaches transmission transistor TX;
Fig. 3…),
a reset transistor (…wherein Lee, in [0043], teaches reset transistor RX; Fig. 3…),
and
a conversion gain transistor disposed on the first semiconductor chip (…wherein in an
embodiment of the pixel PX (image sensor) as depicted in Fig. 12, Lee teaches a
conversion gain transistor DCGT. Further, Lee, in [0023], teaches the image sensor and a
corresponding DSP may be implemented as individual chips …); and
a selection transistor disposed on the second semiconductor chip (…wherein [0055]
teaches selection transistor SX. Lee does not specify that element SX is disposed on a
second semiconductor chip.
However, Moradi, in [0097] with respect to Fig. 6A, teaches a pixel circuit 120 of
substrate 100 with one through contact 915 which connects to a subsequent substrate
200.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that only a specific part of a
photoconversion circuit may be arranged on a first substrate, as taught by Moradi, thus
that of the photodiode remains largely available for light detection in the upper layer of
the image sensor; wherein subsequent circuits are placed on lower layer substrates…).
19. Regarding claim 12, an image sensor (…Lee teaches an image sensor 100 in [0023];
Fig. 1…) comprising:
a first semiconductor chip (…Lee, in [0023], teaches the image sensor (which
extends in intersecting vertical and horizontal directions of Fig. 1) and a corresponding
DSP which may be implemented as individual chips…) including:
a pixel part (…wherein Lee teaches pixel array 110; Fig. 1…) comprising
first and second pixel regions that are adjacent to one other (…wherein the array in
Fig. 1 depicts a row and column of the pixel array…).
Though Lee teaches a circuit part for performing a global shutter operation, on the first
semiconductor chip (…wherein [0029] teaches a row driver which is used to drive control
signals which may be used to cause pixels PX to operate in global shutter mode…); Lee
does not teach that the circuit is disposed on a second semiconductor chip in a vertical direction (…however, Moradi teaches a pixel substrate 100 (Fig. 1) and substrate 200 (wherein the substrates are viewed as being stacked in a vertical direction) wherein element 40 address/driver(control drive signal generator) is contained within element 200.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a pixel substrate could be formed
separate from a substrate that contains a signal driver as taught by Moradi so to
implement the image sensor as taught by Lee, so that maximum area is provided on
substrate of the photodiode for light detection…).
Lee further teaches the image sensor wherein
the pixel part of the first semiconductor chip comprises:
a photodiode (…wherein [0039] (Lee) teaches photodiode PD; Fig. 3…),
a floating diffusion node which accumulates photocharges generated by the photodiode
(…wherein [0042] (Lee) teaches floating diffusion node FD; Fig. 3…), and
a first source follower which amplifies and outputs a signal corresponding to a change in
potential of the floating diffusion node (…wherein [0044] (Lee) teaches source follower SF1
which buffers and amplifies a signal according the potential of FD…),
wherein the circuit part of the second semiconductor chip comprises:
a first pre-charge selection transistor connected between a first node and a second node
(…wherein [0041] teaches PSX1, as a first precharge select transistor connected between
ND1 and ND2; Fig. 3…),
a second pre-charge selection transistor connected to the first pre-charge selection
transistor (…[0042] teaches PSX2, as a second precharge select transistor connected to
PSX1, as depicted in Fig. 3…), and
a pre-charge transistor to pre-charge the second node connected to the first source
follower (…wherein [0041 teaches a precharge transistor PCX; which precharges node
NO2 (which is connected to source follower SF1; Fig. 3…), wherein
the pre-charge transistor comprises:
(…wherein [0120] teaches that pixels may share a first and second precharge
select transistors PSX1 and PSX2; further [0129] teaches that according to an embodiment, a first pixel and a second pixel may share the precharge transistor PCX…);
the following limitations may read on a pixel sharing scheme that may configured wherein a first pre-charge transistor connected to:
a first_1 pre-charge selection transistor of the first pixel region and
a second_1 pre-charge selection transistor of the second pixel region, and
a second pre-charge transistor connected to:
a second_2 pre-charge selection transistor of the first pixel region and
a first_2 pre-charge selection transistor of the second pixel region (…as such any one
of the pixels of array 110 may be configured to be connected to a configuration that may
read on the specifications of the teachings of [0120, 0129]…), and wherein
in a plan view perpendicular to the vertical direction of the image sensor, the first and second precharge transistor of the second semiconductor chip overlap with two or more of the plurality of pixel regions of the first semiconductor chip (…wherein Lee is referenced as teaching a shared transistor between a first and second pixel. Sony further teaches photodiodes and pixel transistors on different substrates stacked “atop the other”.
Additionally, a first and second semiconductor chip, in view of Lee and Sony, in a broad interpretation, can yield different design of circuits which possess the same electronic components.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a shared transistor between two pixels, as taught by Lee, can be implemented through the technology as taught by Sony, wherein photodiodes and transistors are formed on different substrates which are layered atop one another (thus a pixel region of a substrate is in an overlapping relationship with a secondary transistor layer); thus giving an image sensor more dynamic range by increasing saturation signal level….).
20. Regarding claim 14, Lee in view of Sony and Moradi teaches The image sensor of claim 12 (see claim 12 above), wherein
the first and second pre-charge transistors are spaced apart from each other (…wherein
[0129] teaches that the precharge transistor PCX may be shared between a first and a
second pixel; a plurality of such a shared component would have to be arranged in a
manner which would accommodate the pixel array 110 and the multitude of pixels thereof
in either a first or second direction, so to provide each pair of pixels of the array the
shared transistor…).
21. Regarding claim 15, Lee in view of Sony and Moradi teaches the image sensor of claim 12 (see claim 12 above), wherein
first and second active regions in which the first and second pre-charge transistors are
each disposed are spaced apart from each other (…wherein [0129] teaches that the precharge transistor PCX (containing active regions) may be shared between a first and a second pixel; a plurality of such a shared component would have to be arranged in a manner which would accommodate the pixel array 110 and the multitude of pixels thereof in either a first or second direction, so to provide each pair of pixels of the array the shared transistor…).
22. Regarding claim 16, Lee in view of Sony and Moradi teaches the image sensor of claim 15 (see claim 15 above), wherein
a spaced distance between the first and second active regions is greater than a spaced
distance between first and second gates of the first and second pre-charge transistors (…on
the basis that Lee teaches that the precharge transistor PCX may be shared between a
first and a second pixel (as taught in [0129]) and also [0120] teaches that pixels may
share a first and second precharge select transistors PSX1 and PSX2, it may be broadly
reasoned that a shared PCX would extend to a greater length in order to be shared between pixels in a manner which may vary in length to a shared or non-shared PSX1
and PSX2…).
23. Regarding claim 17, Lee in view of Sony and Moradi teaches the image sensor of claim 12 (see claim 12 above), wherein
the circuit part further comprises
a second source follower that amplifies and outputs a signal corresponding to a change
in potential of the first node (…wherein [0054] teaches source follower SF2 which amplifies
a potential change of output node NO1; Fig. 3…), and
an extension length of each of the first and second pre-charge transistors is longer than
an extension length of the second source follower (…on the basis that Lee teaches that the
precharge transistor PCX may be shared between a first and a second pixel (as taught in
[0129]), it may be broadly reasoned that the shared PCX would extend to a greater length
in order to be shared between pixels (in either direction of pixel arrangement and circuit
sharing) and thus have a longer extension than SF2 which is not a shared component a
pixel’s circuitry…).
24. Regarding claim 18, Lee in view of Sony and Moradi teaches the image sensor of claim 12 (see claim 12 above), wherein
the circuit part further comprises:
a first capacitor connected to the first node (…wherein [0041] teaches C1 connected
to NO1 through SAMP1; Fig. 3…), and
a first sampling transistor that samples electric charges to the first capacitor (…wherein
[0050] teaches sampling transistor SAMP1 connected to C1; Fig. 3…),
a second capacitor connected to the first node (…wherein [0052] teaches C2
connected to NO1 through SAMP2; Fig. 3…), and
a second sampling transistor that samples electric charges to the second capacitor
(…wherein [0052] teaches sampling transistor SAMP2 connected to C2…), and
a third capacitor connected to the first node (…wherein Lee, in accordance with Fig.
17, teaches C3 which is connected to a node NO2 (a corresponding node of NO1 of Fig.
3)…), and
a third sampling transistor that samples electric charges to the third capacitor
(…wherein [0143] teaches sampling transistor SAMP3 connected to C3; Fig. 17…).
25. Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et
al. (US 2022/0094864 A1) in view of Nagahama (US 2021/0343776 A1) and further view of Sony (Sony Develops World's First*1Stacked CMOS Image Sensor Technology with 2-Layer Transistor Pixel).
26. Regarding claim 19, an image sensor (…Lee teaches an image sensor 100 in [0023];
Fig. 1…) comprising:
a first substrate (…Lee, in [0023], teaches the image sensor (which extends in
intersecting vertical and horizontal directions of Fig. 1) and a corresponding DSP which
may be implemented as individual chips…) including
a pixel part (…wherein Lee teaches pixel array 110; Fig. 1…) comprising
first and second pixel regions (…wherein the array in Fig. 1 depicts a row and
column of the pixel array…);
a second substrate bonded to the first substrate in a vertical direction through a bonding structure, and including a circuit part connected to the first substrate (…wherein Lee teaches a DSP layer that may be implemented as a separate chip, as taught in [0023], which would be connected to a pixel layer; wherein it is well known in the art that an image sensor comprising two or more substrates is in a stacked formation…).
Lee does not further teach
a third substrate connected to the second substrate, on the second substrate
(…however, Nagahama teaches an image sensor composed of layers including a third substrate wherein a first, second, and the third substrate are stacked and electrically
connected, as taught in [0086] and [0102]; Fig. 1, 7.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that various layers of substrates can be
implemented as taught by Nagahama so that elements which may be placed on a first
substrate (e.g. pixels) may in common share electronic components which are placed on
a secondary substrate (e.g., a transistor) as taught by Nagahama…).
Lee further teaches the pixel part of the first substrate comprises:
a photodiode (…wherein Lee, in [0039], teaches photodiode PD; Fig. 3…),
a floating diffusion node which accumulates photocharges generated by the photodiode
(…wherein Lee, in [0042], teaches floating diffusion node FD; Fig. 3…), and
a first source follower which amplifies and outputs a voltage of the floating diffusion node
(…wherein Lee, in [0044], teaches source follower SF1 which buffers and amplifies a
signal according the potential of FD…), wherein
the circuit part of the substrate comprises:
a first capacitor that stores electric charges according to a voltage of the floating
diffusion node being reset (…wherein Lee, in [0051], teaches that charges from a reset
operation of node FD may be stored in capacitor C1…),
a second capacitor that stores electric charges according to the voltage of the floating
diffusion node in which the photocharges are stored (…wherein Lee, in [0053], teaches that
charges of a photocharge accumulation in the floating diffusion node FD may be stored
in the second capacitor C2…),
a first sampling transistor connected to a first node (…wherein Lee, in [0050], teaches
a first sampling transistor SAMP1 which may be connected to node NO1; Fig. 3…), to sample electric charges to the first capacitor (…wherein sampling transistor SAMP1
connected to C1; Fig. 3…),
a second sampling transistor connected to the first node (…wherein Lee, in [0052],
teaches SAMP2 connected to node NO1; Fig. 3…), to sample electric charge to the second capacitor (…wherein [0052] teaches sampling transistor SAMP2 connected to C2…),
a first pre-charge selection transistor connected between the first node and a second
node (…wherein Lee, in [0041], teaches PSX1, as a first precharge select transistor
connected between ND1 and ND2; Fig. 3…),
a second pre-charge selection transistor connected to the first pre-charge selection
transistor (…wherein Lee, in [0042], teaches PSX2, as a second precharge select
transistor connected to PSX1, as depicted in Fig. 3…), and
a pre-charge transistor which pre-charges the second node connected to the first source
follower (…wherein Lee, in [0041], teaches a precharge transistor PCX; which precharges
node NO2 (which is connected to source follower SF1; Fig. 3…), wherein
in a plan view perpendicular to the vertical direction of the image sensor, the pre-charge transistor of the second substrate overlaps with first and second pixel regions of the first substrate that are adjacent to each other (…wherein Lee, in [0129], teaches that according to an embodiment, a first pixel and a second pixel may share the precharge transistor PCX.
Nagahama, further, teaches an image sensor composed of layers including a first, second, and a third substrate stacked and electrically connected, as taught in [0086]
and [0102]. As such, Fig. 1 depicts a substrate 10 containing pixel circuits and substrate
20 which may have readout circuits arranged thereon. Sony further teaches photodiodes and pixel transistors on different substrates stacked “atop the other”.
Additionally, a first and second semiconductor chip, in view of Lee and Sony, in a broad interpretation, can yield different design of circuits which possess the same electronic components.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that various layers of substrates can be
implemented as taught by Nagahama and Sony, so that elements which may be placed on a first substrate (e.g. pixels) may in common share electronic components which are placed on a secondary substrate (e.g., a transistor) as taught by Nagahama and Sony…).
27. Regarding claim 20, Lee in view of Nagahama and Sony teaches the image sensor of claim 19 (see claim 19 above), wherein
the first pre-charge selection transistor connected to the pre-charge transistor is
disposed in the first pixel region, and the second pre-charge selection transistor connected to
the pre-charge transistor is disposed in the second pixel region (…wherein Lee, in Fig. 1,
teaches a pixel array of a plurality of pixels and regions thereof, Fig. 3 depicts transistor
PCX which may be unique to each pixel and or which also may be shared ([0129]), thus
teaching a plurality of PCX transistors…).
Conclusion
28. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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