DETAILED ACTION
This office action is responsive to communication filed on April 3, 2026.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed March 19, 2026 was received and has been considered by the Examiner.
Response to Arguments
Applicant's arguments filed April 3, 2026 have been fully considered but they are not persuasive.
Applicant argues, with respect to claims 1, 8 and 15, that Ryoki does not disclose, teach or suggest that in the peripheral region of the semiconductor device, at least a portion of the compound semiconductor layer is covered with a protective film.
The Examiner respectfully disagrees. Ryoki teaches that in the peripheral region of the semiconductor device, at least a portion of the compound semiconductor layer (202) is covered with a protective film (The compound semiconductor layer (202) is covered with a planarization layer (209), which is an “inorganic insulating film such as silicon oxide, silicon oxynitride, and silicon nitride, or an organic insulating film such as resin”, as detailed in paragraph 0017 of Ryoki and shown in figure 2A.).
Therefore, the rejection is maintained by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-12 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ryoki (US 2016/0093657).
Consider claim 1, Ryoki teaches:
A semiconductor device (see figures 2A and 2B), comprising:
an upper section including a compound semiconductor layer (The photoelectric conversion film (202) is a “compound semiconductor layer”, as detailed in paragraph 0019.) and a plurality of photoelectric conversion portions (i.e. the photoelectric conversion units (220) of pixels (PIX), figure 2A, paragraph 0018); and
a lower section (wiring structure, 201, substrate, 200, figure 2A, paragraph 0017) including a plurality of circuits (“The substrate 200 includes, for example, a silicon substrate, and includes an element such as a transistor formed thereon. In the present embodiment, the elements include a storage capacitor 205, an amplification transistor 208, and a reset transistor 207. These elements constitute the reading circuit of the pixel PIX.” paragraph 0017), the upper section and the lower section (201, 200) being stacked (see figure 2A) and each of the plurality of photoelectric conversion portions (220) and each of the plurality of circuits being coupled via electrodes (e.g. via first electrodes, 203, paragraph 0018, see figure 2A),
wherein, in a peripheral region of the semiconductor device (see figures 2A and 2B), a voltage is applied to at least one of the plurality of the photoelectric conversion portions (i.e. by applying a voltage (ΦVp) to a second electrode (204) of at least one of the photoelectric conversion portions (220), paragraphs 0024 and 0025); and
wherein, in the peripheral region of the semiconductor device, at least a portion of the compound semiconductor layer (202) is covered with a protective film (The compound semiconductor layer (202) is covered with a planarization layer (209), which is an “inorganic insulating film such as silicon oxide, silicon oxynitride, and silicon nitride, or an organic insulating film such as resin”, as detailed in paragraph 0017 of Ryoki and shown in figure 2A.).
Consider claim 2, and as applied to claim 1 above, Ryoki further teaches that in the peripheral region of the semiconductor device (see figures 2A and 2B), at least a portion of the compound semiconductor layer (202) is covered with a metal film (second electrode, 204, paragraph 0018).
Consider claim 3, and as applied to claim 2 above, Ryoki further teaches that the voltage (ΦVp) is applied to the metal film (204, see paragraph 0024).
Consider claim 4, and as applied to claim 1 above, Ryoki further teaches that the compound semiconductor layer (202) includes gallium arsenide (GaAs) (“As still another exemplary material for the photoelectric conversion film 202, the quantum dot layer includes, for example, a buffer material such as ALGAAS or GAAS” paragraph 0019).
Consider claim 5, and as applied to claim 2 above, Ryoki further teaches that the metal film (204) is selected from the group that includes tungsten (W), aluminum (Al) and gold (Au) (“the second electrode 204 include, for example, aluminum” paragraph 0018).
Consider claim 8, Ryoki teaches:
A semiconductor device (see figures 2A and 2B), comprising:
a compound semiconductor layer (The photoelectric conversion film (202) is a “compound semiconductor layer”, as detailed in paragraph 0019.) and a plurality of photoelectric conversion portions (i.e. the photoelectric conversion units (220) of pixels (PIX), figure 2A, paragraph 0018); and
a silicon substrate (wiring structure, 201, substrate, 200, figure 2A, paragraph 0017) including a plurality of circuits (“The substrate 200 includes, for example, a silicon substrate, and includes an element such as a transistor formed thereon. In the present embodiment, the elements include a storage capacitor 205, an amplification transistor 208, and a reset transistor 207. These elements constitute the reading circuit of the pixel PIX.” paragraph 0017), the compound semiconductor layer (202) and the silicon substrate (201, 200) being stacked (see figure 2A), and each of the plurality of photoelectric conversion portions (220) and each of the plurality of circuits being coupled via electrodes (e.g. via first electrodes, 203, paragraph 0018, see figure 2A),
wherein, in a peripheral region of the semiconductor device (see figures 2A and 2B), a voltage is applied to at least one of the plurality of the photoelectric conversion portions (i.e. by applying a voltage (ΦVp) to a second electrode (204) of at least one of the photoelectric conversion portions (220), paragraphs 0024 and 0025); and
wherein, in the peripheral region of the semiconductor device, at least a portion of the compound semiconductor layer (202) is covered with a protective film (The compound semiconductor layer (202) is covered with a planarization layer (209), which is an “inorganic insulating film such as silicon oxide, silicon oxynitride, and silicon nitride, or an organic insulating film such as resin”, as detailed in paragraph 0017 of Ryoki and shown in figure 2A.).
Consider claim 9, and as applied to claim 8 above, Ryoki further teaches that in the peripheral region of the semiconductor device (see figures 2A and 2B), at least a portion of the compound semiconductor layer (202) is covered with a metal film (second electrode, 204, paragraph 0018).
Consider claim 10, and as applied to claim 9 above, Ryoki further teaches that the voltage (ΦVp) is applied to the metal film (204, see paragraph 0024).
Consider claim 11, and as applied to claim 8 above, Ryoki further teaches that the compound semiconductor layer (202) includes gallium arsenide (GaAs) (“As still another exemplary material for the photoelectric conversion film 202, the quantum dot layer includes, for example, a buffer material such as ALGAAS or GAAS” paragraph 0019).
Consider claim 12, and as applied to claim 9 above, Ryoki further teaches that the metal film (204) is selected from the group that includes tungsten (W), aluminum (Al) and gold (Au) (“the second electrode 204 include, for example, aluminum” paragraph 0018).
Consider claim 15, Ryoki teaches:
A semiconductor device (see figures 2A and 2B), comprising:
an upper section including a compound semiconductor layer (The photoelectric conversion film (202) is a “compound semiconductor layer”, as detailed in paragraph 0019.) and a plurality of photoelectric conversion portions (i.e. the photoelectric conversion units (220) of pixels (PIX), figure 2A, paragraph 0018); and
a lower section (wiring structure, 201, substrate, 200, figure 2A, paragraph 0017) including a plurality of circuits (“The substrate 200 includes, for example, a silicon substrate, and includes an element such as a transistor formed thereon. In the present embodiment, the elements include a storage capacitor 205, an amplification transistor 208, and a reset transistor 207. These elements constitute the reading circuit of the pixel PIX.” paragraph 0017), the upper section and the lower section (201, 200) being stacked (see figure 2A) and each of the plurality of photoelectric conversion portions (220) and each of the plurality of circuits being coupled via electrodes (e.g. via first electrodes, 203, paragraph 0018, see figure 2A),
wherein, in a peripheral region of the semiconductor device (see figures 2A and 2B), at least a portion of the compound semiconductor layer (202) is covered with a protective film (The compound semiconductor layer (202) is covered with a planarization layer (209, i.e. protective film), which is an “inorganic insulating film such as silicon oxide, silicon oxynitride, and silicon nitride, or an organic insulating film such as resin”, as detailed in paragraph 0017 of Ryoki and shown in figure 2A.) and a metal film (The compound semiconductor layer (202) is covered with an upper electrode film (204, paragraph 0018) which is comprised of aluminum (paragraph 0018).).
Consider claim 16, and as applied to claim 15 above, Ryoki further teaches that the voltage (ΦVp) is applied to the metal film (204, see paragraph 0024).
Consider claim 17, and as applied to claim 15 above, Ryoki further teaches that the compound semiconductor layer (202) includes gallium arsenide (GaAs) (“As still another exemplary material for the photoelectric conversion film 202, the quantum dot layer includes, for example, a buffer material such as ALGAAS or GAAS” paragraph 0019).
Consider claim 18, and as applied to claim 15 above, Ryoki further teaches that the metal film (204) is selected from the group that includes tungsten (W), aluminum (Al) and gold (Au) (“the second electrode 204 include, for example, aluminum” paragraph 0018).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 7, 13, 14, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ryoki (US 2016/0093657) in view of Nagano et al. (US 2014/0291486).
Consider claims 6 and 7, and as applied to claim 1 above, Ryoki does not explicitly teach that the electrodes include bump electrodes provided between connection electrodes.
Nagano et al. similarly teaches a semiconductor device (figure 2) including a light detection element (10A) connected to a mounting substrate (20, paragraphs 0026, 0027 and 0043) via electrodes (E7, BE, E9, paragraphs 0032, 0036, 0039 and 0041).
However, Nagano et al. additionally teaches that the electrodes include bump electrodes (bump electrodes, BE, paragraphs 0041 and 0042) provided between connection electrodes (E7 and E9, see figure 2, paragraph 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the electrodes taught by Ryoki include bump electrodes provided between connection electrodes as taught by Nagano et al. as this simply involves combining prior art elements according to known methods to yield predictable results such as enabling readout of image signals for signal processing (Nagano et al., paragraph 0045).
Consider claims 13 and 14, and as applied to claim 8 above, Ryoki does not explicitly teach that the electrodes include bump electrodes provided between connection electrodes.
Nagano et al. similarly teaches a semiconductor device (figure 2) including a light detection element (10A) connected to a mounting substrate (20, paragraphs 0026, 0027 and 0043) via electrodes (E7, BE, E9, paragraphs 0032, 0036, 0039 and 0041).
However, Nagano et al. additionally teaches that the electrodes include bump electrodes (bump electrodes, BE, paragraphs 0041 and 0042) provided between connection electrodes (E7 and E9, see figure 2, paragraph 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the electrodes taught by Ryoki include bump electrodes provided between connection electrodes as taught by Nagano et al. as this simply involves combining prior art elements according to known methods to yield predictable results such as enabling readout of image signals for signal processing (Nagano et al., paragraph 0045).
Consider claims 19 and 20, and as applied to claim 15 above, Ryoki does not explicitly teach that the electrodes include bump electrodes provided between connection electrodes.
Nagano et al. similarly teaches a semiconductor device (figure 2) including a light detection element (10A) connected to a mounting substrate (20, paragraphs 0026, 0027 and 0043) via electrodes (E7, BE, E9, paragraphs 0032, 0036, 0039 and 0041).
However, Nagano et al. additionally teaches that the electrodes include bump electrodes (bump electrodes, BE, paragraphs 0041 and 0042) provided between connection electrodes (E7 and E9, see figure 2, paragraph 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the electrodes taught by Ryoki include bump electrodes provided between connection electrodes as taught by Nagano et al. as this simply involves combining prior art elements according to known methods to yield predictable results such as enabling readout of image signals for signal processing (Nagano et al., paragraph 0045).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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