Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed February 20, 2026 have been fully considered but they are not persuasive.
In page 1 of the remarks, Applicant states that the claims 1-20 were rejected under 35 U.S.C. 112(b) (“112(b)”) as indefinite, as the terms “device specific data” was rejected. Applicant states that the term “device specific data” is defined in the Merriam-Webster dictionary as “restricted to a particular individual”, and may be defined as data that is restricted to a particular device. Applicant requests withdrawal of the rejections under 112(b) as the term “device specific data” is consistent with the use of the term within the Application in the field.
Examiner disagrees with the Applicant regarding the use of “device specific data”, as Applicant does not specify where in the Specification the term is defined, as while paragraph [0052] states that the extensible firmware interface (EFI) system partition (ESP) 334 contains device driver files for hardware devices present in its associated information handling system (IHS) 100 used by firmware at boot time, the lack of a definition for the term “device specific data” in the Specification does not clear up the indefiniteness of the term in the application. As a result, Examiner maintains the 112(b) rejection for claims 1-20 regarding the use of the term “device specific data” remaining indefinite in the invention of the Applicant.
In pages 1-2 of the remarks, Applicant states that the claims 1-20 were rejected under 35 U.S.C. 103 (“103”) as unpatentable over Suryanarayana et al. (US 20200394303 A1) (“Suryana”) in view of Terpstra et al. (US 20230229778 A1) (“Terpstra”). Applicant states that the element of providing an information handling system (IHS) with a distributed BIOS, Examiner cites to Suryana, in particular paragraph [0018] disclosing a BIOS code which is compliant with the Unified Extensible Firmware Interface (UEFI) where a firmware image can be customized, but states that a distributed BIOS of the invention is distinct from the BIOS disclosed in Suryana. Applicant further states that Suryana does not suggest a distributed BIOS being implemented to function with any of a plurality of processor environments, as required by the independent claims, and the deficiency of Suryana is not cured by Terpstra.
Examiner disagrees with the Applicant regarding the lack of suggestion from either Suryana or Terpstra for the amended limitation in the independent claims 1, 7, and 13 of “the distributed BIOS being implemented to function with any of a plurality of processor environments”, as Suryana describes in paragraph [0014] Platform security processor (PSP) 174 (associated with AMD x86 processors) and/or a management engine (ME) 176 (associated with Intel x86 processors) operate independently of core processors at CPU 102, and execute firmware prior to execution of BIOS by a primary CPU core processor, which allows a distributed BIOS to be implemented to function with a plurality of processor environments. Paragraph [0018] of Suryana describes the firmware as being configurable, as the BIOS can be compliant with one or more revision of the UEFI specification, and the specification can manage initialization and configuration of devices with the BIOS, which also includes components of the system 100 being configured and enabled for operation during an initialization sequence of the BIOS, as described in paragraph [0019]. Therefore, the BIOS of Suryana is equivalent to the distributed BIOS of the Applicant, which can also be configurable with BIOS variables, as described in paragraph [0023] of the Specification of the Applicant. Furthermore, the Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Furthermore, in page 2 of the remarks, it is stated that the element of enumerating a trusted port via a trusted queue management operation is cited to Terpstra by the Examiner, but that the disclosed trusted queue management operation is distinct from the authenticating and provisioning devices suggested in Terpstra. Applicant also states that the amended limitation in the independent claims 1, 7, and 13 of “enumerating a trusted port […] the trusted queue management operation generating and managing a trusted work queue, […] being protected from a malicious attack”, as required by independent claims 1, 7, and 13.
Examiner disagrees with the Applicant regarding the lack of suggestion from either Suryana or Terpstra for the amended limitation in the independent claims 1, 7, and 13 of “the trusted queue management operation generating and managing a trusted work queue, the trusted work queue being protected from a malicious attack” is suggested by Suryana in paragraph [0027] Successfully authenticated firmware images, such as images 332 and 333, are each stored at System Firmware at NVMe Namespace 330, as shown in Fig. 3, wherein it is described as a protected System Firmware. Runtime services, including runtime authentication of firmware images, utilizes protected memory space at memory 104 associated with the IHS 100, corresponds to a trusted work queue protected from malicious attacks, as [0027] further states that normal runtime programs cannot access protected memory space at memory 104, where a traditional UEFI capsule update method has been vulnerable to various malicious attacks as described in paragraph [0021]. Furthermore, the Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. As a result, Examiner maintains the 103 rejections for claims 1-20 over Suryana in view of Terpstra.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “device specific data” in claim 1, line 4 is a relative term which renders the claim indefinite. The term “device specific data” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Although paragraph [0052] in the Specification of the Applicant that an extensible firmware interface (EFI) system partition (ESP) 334 contains device driver files for hardware devices present in its associated information handling system (IHS) 100 used by firmware at boot time, the Specification does not provide a standard as to what ‘device specific data’ is to be identified, nor does the Specification provide a definition for which devices are identified for ‘device specific data’ in the context of an information handling system (IHS).
Dependent claims 2-6 are rejected for relying upon independent claim 1, and inherit the rejections of their respective independent claim 1 above.
The term “low memory region of memory” in claim 6, lines 2-3 is a relative term which renders the claim indefinite. The term “low memory portion of memory” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. While “lower main memory 112” is defined as “(e.g. 1MB to 1GB)” in paragraph [0025] in the Specification of the Applicant, and “low memory region” stores individual flash memory packets in paragraph [0061] in the Specification of the Applicant, it is not made clear in the claims that this is the case, as well as whether the “lower main memory 112” in the Specification is the same as the “low memory portion of memory” present in claim 6 or a different use of the term.
Independent claim 7 shares limitations that are present in independent claim 1 above, and inherits the rejections of independent claim 1 above.
Dependent claims 8-12 are rejected for relying upon independent claim 7, and inherit the rejections of their respective independent claim 7 above.
Dependent claim 12 shares limitations that are present in dependent claim 6 above, and inherits the rejections of dependent claim 6 above.
Independent claim 13 shares limitations that are present in independent claim 1 above, and inherits the rejections of independent claim 1 above.
Dependent claims 14-20 are rejected for relying upon independent claim 13, and inherit the rejections of their respective independent claim 13 above.
Dependent claim 18 shares limitations that are present in dependent claim 6 above, and inherits the rejections of dependent claim 6 above.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the disclosure regarding how the inventor intended to perform the claimed limitation of 'identifying device specific data associated with a device of the information handling system' in claim 1, as paragraph [0052] describes that an extensible firmware interface (EFI) system partition, or ESP 334, may be implemented to contain boot loaders, device driver files for hardware devices present in its associated IHS, and other information associated with the IHS. While paragraph [0074] also describes an Advanced Configuration and Power Interface (ACPI) Source Language (ASL) node, not shown, is used to translate interactions into device-specific methods linked to secure, trusted ports 622, at no point in the Specification of the Applicant is there a process on how the invention identifies device-specific data, such as device driver files for hardware devices present in an associated IHS which are stored in the ESP 334, as stated in paragraph [0052]. Furthermore, paragraphs [0003]-[0005] merely restate the limitations of the claim without explaining details as to how identification of device specific data associated with a device functions or is performed. As a result, the Specification does not support Applicant’s limitation of 'identifying device specific data associated with a device […]' in claim 1 functions in sufficient detail. The algorithm or steps/procedures for these claimed functions is not explained at all or is not explained in sufficient detail (simply restating the function reciting in the claim is not necessarily sufficient) so that one of ordinary skill in the art would recognize that the applicant had possession of the full scope of the claimed invention.
Dependent claims 2-6 are rejected for relying upon independent claim 1, and inherit the rejections of their respective independent claim 1 above.
Independent claim 7 shares limitations that are present in independent claim 1 above, and inherits the rejections of independent claim 1 above.
Dependent claims 8-12 are rejected for relying upon independent claim 7, and inherit the rejections of their respective independent claim 7 above.
Independent claim 13 shares limitations that are present in independent claim 1 above, and inherits the rejections of independent claim 1 above.
Dependent claims 14-20 are rejected for relying upon independent claim 13, and inherit the rejections of their respective independent claim 13 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suryana in view of Terpstra et al. (US 20230229778 A1), hereinafter Terpstra.
Regarding claim 1, Suryana discloses ‘a computer-implementable method for performing a firmware management operation, comprising: providing an information handling system with a distributed BIOS, the distributed BIOS being implemented to function with any of a plurality of processor environments’ ([0028] Fig. 4, blocks 401 and 402. Paragraph [0018] describes the firmware as being configurable, corresponding to a distributed BIOS of the Applicant. [0014] Platform security processor (PSP) 174 (associated with AMD x86 processors) and/or a management engine (ME) 176 (associated with Intel x86 processors) operate independently of core processors at CPU 102, and execute firmware prior to execution of BIOS by a primary CPU core processor, which allows a distributed BIOS to be implemented to function with a plurality of processor environments.);
‘identifying device specific data associated with a device of the information handling system’ ([0028] Fig. 4, block 403, a non-volatile storage media is identified, and the storage media is associated with a device of the information handling system ("IHS") 100.);
‘the trusted queue management operation generating and managing a trusted work queue, the trusted work queue being protected from a malicious attack’ ([0027] Successfully authenticated firmware images, such as images 332 and 333, are each stored at System Firmware at NVMe Namespace 330, as shown in Fig. 3, wherein it is described as a protected System Firmware. Runtime services, including runtime authentication of firmware images, utilizes protected memory space at memory 104 associated with the IHS 100, corresponds to a trusted work queue protected from malicious attacks, as [0027] further states that normal runtime programs cannot access protected memory space at memory 104, where a traditional UEFI capsule update method has been vulnerable to various malicious attacks as described in paragraph [0021].);
‘and, authorizing device specific communication, the device specific communication using a device-specific buffer handling operation’ ([0028] When firmware image is authenticated, the identified NVMe stores the firmware image, which the NVMe is identified by firmware interface table (FIT) 320, accessed by an Advanced Configuration and Power Interface (ACPI) runtime service, which also has handler events 301 triggered by executing a firmware update package, stated by [0026]. [0027] Successfully authenticated firmware images, such as images 332 and 333, are each stored at System Firmware at NVMe Namespace 330, as shown in Fig. 3.).
Suryana does not appear to teach, but Terpstra teaches ‘enumerating a trusted port via a trusted queue management operation’ ([0147] Fig. 19, devices are registered to SDO service, find owner location, and devices are authenticated, shown in steps 3-5. Each device authenticated and provisioned corresponds to enumerating a trusted port via a trusted queue management operation. [0122] Fig. 11, onboarding server 1116 maintains queue for communications sequence of responses and replies until a final required action has been completed between control plane 1101 and edge device(s) 1103.);
and ‘authorizing device specific communication via the trusted port, the device specific communication’ ([0052] Fig. 2, step 202, system update handler handles provisioning of a secured runtime OS on the at least one processing device. In paragraph [0054], an authenticated device can receive one or more payloads that are deployed and/or processed, and there can be a delay of time between receipt of a given payload and deployment of another payload, which acts as a buffer handling operation.);
Therefore, one of ordinary skill in the art would have been capable of applying this known method of ‘enumerating a trusted port via trusted queue management operation’ and ‘authorizing device specific communication via the trusted port’ in an information handling system for firmware management operation and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure that devices are trusted in a zero-trust environment to provision devices in the multi-phase secure zero touch provisioning (MPSZTP) to be securely onboarded for provisioning of edge devices (Terpstra, [0058]).
Regarding claim 2, Suryana in view of Terpstra teach the method of claim 1 as recited above. Suryana further discloses ‘wherein: the information handling system includes an embedded controller, the embedded controller being implemented to enable a BIOS root of trust’ ([0014] EC 190 provides aspects of a hardware root of trust, which ensures that firmware and other software necessary for operation of an IHS is operating as intended.).
Regarding claim 3, Suryana in view of Terpstra teach the method of claim 1 as recited above. Suryana does not appear to teach, but Terpstra teaches ‘wherein: the trusted port is generated via a secure enclave protocol’ ([0058] Multi-phase secure zero touch provisioning ("MPSZTP") enables computing devices to be securely on-boarded and provisioned in a zero-trust environment. Performs this by establishing and maintaining a known trusted state for each edge computing device.);
‘and, the secure enclave protocol uses the BIOS root of trust when generating the trusted port’ ([0038] Such provisioning includes digitally signing the image of secured runtime OS utilizing hardware-based root of trust of the edge device.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of generating a trusted port via a secure enclave protocol, which uses the BIOS root of trust to manage firmware in an information handling system and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to utilize multi-phase secure zero touch provisioning (MPSZTP) and recovery, with MPSZTP processes used for onboarding of edge computing devices located at various sites, with onboarding enabled via installation of a firmware-based tool to provision edge devices with firmware (Terpstra, [0058]).
Regarding claim 4, Suryana in view of Terpstra teach the method of claim 1 as recited above. Suryana in view of Terpstra teach the method of claim 3 recited above, and Suryana further discloses ‘wherein: a device specific buffer handling protocol is used to generate a dedicated protected queue, the dedicated protected queue being associated with the device specific data of the device of the information handling system’ ([0028] Non-volatile device provides temporary storage of the new image(s) to be used in a subsequent boot sequence to update corresponding device images. [0027] Successfully authenticated firmware images, such as images 332 and 333, are each stored at System Firmware at NVMe Namespace 330, as shown in Fig. 3, wherein it is described as a protected System Firmware. Runtime services, including runtime authentication of firmware images, utilizes protected memory space at memory 104 associated with the IHS 100, corresponds to a dedicated protected queue of the Applicant.).
Regarding claim 5, Suryana in view of Terpstra teach the method of claim 1 as recited above. Suryana does not appear to teach, but Terpstra teaches ‘wherein: runtime device-specific communications use a secure, zero trust runtime secure enclave’ ([0031] MPSZTP logic facilitates provisioning though secure communication with control plane 120 as the management computing site 102. [0058] MPSZTP process described can provision devices in a zero-trust environment, MPSZTP corresponding to a secure, zero trust runtime secure enclave.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of establishing runtime device-specific communications that use a secure, zero trust runtime secure enclave to assist in managing firmware in an information handling system and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure that network transport operations take place over a secured connection, such as a Virtual Private Network (VPN), Internet Protocol Security (IPsec), but the preferred approach for a zero trust environment utilizes encrypted Virtual Local Area Network (VLAN), with network connections also uses session-level encryption, including but not limited to Secure Shell (SSH), Transport Layer Security (TLS), and other types of encryption connections (Terpstra [0106]).
Regarding claim 6, Suryana in view of Terpstra teach the method of claim 1 as recited above. Suryana in view of Terpstra teach the method of claim 3 recited above, and Suryana further discloses ‘wherein: the runtime enclave protects a low memory region of memory of the information handling system’ ([0027] Runtime services utilize protected memory space at memory 104 in IHS 100, protected memory space is not accessible by normal runtime programs.).
Suryana does not fully disclose, but Terpstra teaches a ‘the secure, zero trust runtime secure enclave’ ([0123] MPSZTP processing conforms to Zero Trust Architecture as defined by NIST SP-800-207. [0041] Memory implements at least a portion of the functionality of MPSZTP logic 122 and 142 in Control Plane 120 and Edge Device(s) 140, respectively.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of establishing secure, zero trust runtime secure enclave to assist in managing firmware with regards to a runtime enclave protecting a low memory region of memory portion of memory in an information handling system and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to maintain a hardware-based root of trust, such as through firmware-based onboarding and deployment, having the ability to sign trusted OS images with a hardware secure key for pre-boot time OS attestation and validation (Terpstra [0125]), and implements a portion of memory to functionality of MPSZTP logic (Terpstra [0041]).
Regarding claim 7, Suryana in view of Terpstra teach similar limitations also present in independent claim 1, and Suryana also discloses ‘system comprising: a processor; a data bus coupled to the processor; and a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for’ ([0015] Fig. 1, CPU 102 can be coupled to NVMe 190 that is interfaced via ATA bus 122. ATA corresponds to a data bus as it couples the two components together. [0036] Computer-readable medium includes any medium capable of storing a set of instructions executable by a processor to perform any one or more methods or operations disclosed in Suryana.).
Regarding claim 8, Suryana in view of Terpstra teach the system of claim 7 as recited above. Suryana also discloses similar limitations present in dependent claim 2 above.
Regarding claim 9, Suryana in view of Terpstra teach the system of claim 7 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 3 recited above.
Regarding claim 10, Suryana in view of Terpstra teach the system of claim 7 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 4 recited above.
Regarding claim 11, Suryana in view of Terpstra teach the system of claim 7 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 5 recited above.
Regarding claim 12, Suryana in view of Terpstra teach the system of claim 7 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 6 recited above.
Regarding claim 13, Suryana in view of Terpstra teach similar limitations also present in independent claim 1, and Suryana also discloses ‘a non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for’ ([0036] Computer-readable medium includes any medium capable of storing a set of instructions executable by a processor to perform any one or more methods or operations disclosed in Suryana.).
Regarding claim 14, Suryana in view of Terpstra teach the non-transitory, computer-readable storage medium of claim 7 as recited above. Suryana also discloses similar limitations present in dependent claim 2 above.
Regarding claim 15, Suryana in view of Terpstra teach the non-transitory, computer-readable storage medium of claim 13 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 3 recited above.
Regarding claim 16, Suryana in view of Terpstra teach the non-transitory, computer-readable storage medium of claim 13 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 4 recited above.
Regarding claim 17, Suryana in view of Terpstra teach the non-transitory, computer-readable storage medium of claim 13 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 5 recited above.
Regarding claim 18, Suryana in view of Terpstra teach the non-transitory, computer-readable storage medium of claim 13 as recited above. Suryana in view of Terpstra teach the limitations also present in dependent claim 6 recited above.
Regarding claim 19, Suryana in view of Terpstra teach the computer-readable storage medium of claim 13 as recited above. Suryana does not fully disclose, but Terpstra teaches ‘wherein: the computer executable instructions are deployable to a client system from a server system at a remote location’ ([0127] MPSZTP processing provides ability to deploy, attest, and provision computing devices remotely.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of using computer executable instructions that are deployable to a client system from a server system at a remote location to assist in managing firmware and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to provide processing of MPSZTP logic to lower customer costs though elimination of System Integration overheads, with no IT staff needing to be present while the process is running, as well as self-healing of deployed devices being available (Terpstra [0127]).
Regarding claim 20, Suryana in view of Terpstra teach the computer-readable storage medium of claim 13 as recited above. Suryana does not fully disclose, but Terpstra teaches ‘wherein: the computer executable instructions are provided by a service provider to a user on an on-demand basis’ ([0121] Fig. 11, Upon request from edge device(s) 1103, Onboarding server 1116 and provisioning system 1112 provide a REST API-based service to the edge device(s).).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of using computer executable instructions are provided by a service provider to a user on an on-demand basis to assist in managing firmware and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to utilize firmware agents in edge devices to provide functionality for processing requests from a control plane, located remotely in a server, to call home to deliver current status updates, and receive further update bundles of software and/or instructions (Terpstra [0116]), and having a server implementing a REST API-based service to receive and process incoming requests from edge devices (Terpstra [0118]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.M./ Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/ Supervisory Patent Examiner, Art Unit 2496