Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the application filed 25 July 2024. Claims 1-14 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25 July 2024 is being considered by the examiner.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6-12, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Oshima (US 2022/0188617 A1, hereinafter "Oshima").
Regarding Claim 1, Oshima teaches:
A node (Oshima, Fig. 5, and [0066]: "FIG. 5 shows a configuration of a neuron circuit of a reservoir unit in the reservoir computer of the present embodiment. In the present embodiment, a cyclic type analog-to-digital conversion circuit is applied as the analog-to-digital conversion circuit 106 in the first embodiment, and the analog-to-digital conversion circuit 106 is configured with a capacitor array circuit unit, a non-linear amplifier, and a buffer") comprising a first input terminal, a second input terminal (Oshima, [0036]: "A plurality of analog differential signals are input to a capacitor array circuit unit (CAPARY) 101. The input signals are analog output signals of another neuron circuit, an analog output signal of the neuron circuit itself, or an analog input signal from the outside," where Oshima's outside signal corresponds to first input and neural circuit output corresponds to the instant second input), a first sample and hold circuit (Oshima, Fig. 5, depicting CAPARY 501 corresponding to the instant sample/hold circuit per [0013]: "The capacitor memory circuit has two lanes, each lane including a capacitor for storing and a switch. Each of the lanes is capable of sampling a result of the non-linear calculation output from the amplifier, storing the result as an electric charge in the capacitor for storing, and supplying a voltage to the buffer circuit based on the stored electric charge"), and a first output terminal (Oshima, Fig. 5 depicting output terminal AOP corresponding a first output terminal, per [0040]: "Differential outputs (AOP, AON) of the buffer 105 are analog outputs of the neuron circuit and are input to the other neuron circuit or the neuron circuit itself"),
wherein the first input terminal is configured to be connectable to an input source for transmitting an input signal to a reservoir device (Oshima, Fig. 5, depicting analog input INP3 corresponding to the instant first input terminal, per [0036]: "A plurality of analog differential signals are input to a capacitor array circuit unit (CAPARY) 101. The input signals are ... an analog input signal from the outside. ... [F]or example, three differential signals (INP1, INN1), (INP2, INN2), and (INP3, INN3) are input to the capacitor array circuit unit 101" and [0066]: "FIG. 5 shows a configuration of a neuron circuit of a reservoir unit in the reservoir computer of the present embodiment" and [0067]: "Similar to the first embodiment, a plurality of differential signals are input to a capacitor array circuit unit 501"),
wherein the second input terminal is configured to be connectable to at least one other node (Oshima, Fig. 5, depicting analog input INP3 corresponding to the instant second input terminal, per [0036]: "A plurality of analog differential signals are input to a capacitor array circuit unit (CAPARY) 101. The input signals are analog output signals of another neuron circuit .... [F]or example, three differential signals (INP1, INN1), (INP2, INN2), and (INP3, INN3) are input to the capacitor array circuit unit 101" and [0066]: "FIG. 5 shows a configuration of a neuron circuit of a reservoir unit in the reservoir computer of the present embodiment" and [0067]: "Similar to the first embodiment, a plurality of differential signals are input to a capacitor array circuit unit 501"),
wherein a first terminal of the first sample and hold circuit is connected to the first input terminal and the second input terminal (Oshima, Fig. 5, depicting input terminals to CAPARY 501 and first terminal between CAPARY 501 and NLBF 502, and [0067]: "a plurality of differential signals are input to a capacitor array circuit unit 501, and the capacitor array circuit unit 501 outputs product-sum calculation results for those inputs. The output of the capacitor array circuit unit 501 is input to a non-linear amplifier/buffer (NLBF) 502"),
wherein a second terminal of the first sample and hold circuit is connected to the first output terminal (Oshima, Fig. 5, depicting second terminal between capacitor 507 and switch 511),
wherein the first output terminal is configured to be connectable to at least one other node (Oshima, Fig. 5, depicting output terminal AOP corresponding to the instant first output terminal, per [0040]: "Differential outputs (AOP, AON) of the buffer 105 are analog outputs of the neuron circuit and are input to the other neuron circuit or the neuron circuit itself" and [0061]: "each of the neuron circuits has an analog output and a digital output, and the analog output (not shown in FIG. 4) is input to another neuron circuit or the neuron circuit itself"), and
wherein the first sample and hold circuit holds and converts a joined signal of the input signal and a propagated signal from the second input terminal (Oshima, Figs. 5 and 6, depicting multiple inputs to 501 being combined and passed to NLBF 502, where unit 501 performs conversion by amplification, as in [0073]: "sampling and the residual amplification are performed by the capacitor array circuit unit 501").
Regarding Claim 12, Oshima teaches:
A reservoir device comprising a plurality of nodes, wherein at least one of the plurality of nodes is the node according to claim 1 (Oshima, Fig. 5, and [0066]: "FIG. 5 shows a configuration of a neuron circuit of a reservoir unit in the reservoir computer of the present embodiment. In the present embodiment, a cyclic type analog-to-digital conversion circuit is applied as the analog-to-digital conversion circuit 106 in the first embodiment, and the analog-to-digital conversion circuit 106 is configured with a capacitor array circuit unit, a non-linear amplifier, and a buffer").
Regarding Claim 2, the rejection of Claim 1 is incorporated. Oshima teaches:
wherein the first sample and hold circuit includes a first switch (Oshima, Fig. 6, depicting switch 611 corresponding to instant first switch), a second switch (Oshima, Fig. 9, depicting switch 509 corresponding to instant second switch), a first capacitor (Oshima, Fig. 6, depicting capacitor 605 corresponding to instant first capacitor), a second capacitor (Fig. 5, depicting capacitor 507 corresponding to the second capacitor), and an amplification circuit (Oshima, Fig. 5, depicting NLBF 502 corresponding to instant amplification circuit), wherein the first switch is disposed between the first terminal and the first capacitor (Oshima, Fig. 6, depicting switch 611 between terminal at IPM and capacitor 605), wherein the first capacitor is disposed between the first switch and the second switch (Oshima, Fig. 6, depicting capacitor 605 between switches 611 and 509), wherein the second switch is disposed between the first capacitor and the second capacitor (Oshima, Figs. 5 and 6, depicting switch 509 between capacitor 605 and capacitor 507), wherein the second capacitor is disposed between the second switch and the second terminal (Oshima, Fig. 5, depicting capacitor 507 between switch 509 and second terminal before switch 511), and wherein the amplification circuit is connected to the first capacitor and amplifies a potential of the first capacitor (Oshima, [0037]: "The capacitor array circuit unit 101 performs a product-sum calculation. The output of the capacitor array circuit unit 101 is input to a non-linear amplifier (NLA) 102. The non-linear amplifier 102 is a general differential amplifier and amplifies linearly with respect to a small input voltage, but as the input voltage increases, the increase in an output voltage becomes gradual due to saturation characteristics of the amplifier").
Regarding Claim 4, the rejection of Claim 2 is incorporated. Oshima teaches:
wherein the second switch is turned off when the first switch is turned on, and wherein the first switch is turned off when the second switch is turned on (Oshima, Fig. 5 and 6, depicting first input switch 611 being on during sampling and off during calculation, and second buffer charging switch 509 being off, and vice versa, as in [0077]: "The non-linear amplifier/buffer 502 operates as a buffer this time and differentially outputs a voltage equal to the differential output voltage. At this time, the switches 509 and 510 are turned on" and [0078]: "After the capacitor is fully charged, the switches 509 and 510 are turned off and electric charges are sampled on the capacitors 507 and 508" and [0131]: "During the period, switches 607 to 612 of the capacitor array circuit unit 501 are turned off to block an input signal of the neuron circuit").
Regarding Claim 6, the rejection of Claim 1 is incorporated. Oshima teaches:
a second output terminal connected to the second terminal, wherein the second output terminal is configured to be connectable to a read-out for outputting a signal to outside of the reservoir device (Oshima, Fig. 5, depicting digital output 513 corresponding to the instant second output terminal, which is connected to the second terminal by means of switch 511, and outputting the result of the node and entire circuit, as in [0080]: "The digital correction unit 513 is implemented as a digital integrated circuit, performs a correction calculation by a generally known method using the digital value, and inputs a result (DO) to an output layer as an output of the analog-to-digital conversion circuit").
Regarding Claim 7, the rejection of Claim 6 is incorporated. Oshima teaches:
a third switch that is disposed between the second output terminal and the second terminal (Oshima, Fig. 5, depicting switch 511 corresponding to the instant third switch).
Regarding Claim 8, the rejection of Claim 1 is incorporated. Oshima teaches:
a nonlinear circuit, wherein the nonlinear circuit is connected to the second terminal and the first output terminal (Oshima, [0037]: "The capacitor array circuit unit 101 performs a product-sum calculation. The output of the capacitor array circuit unit 101 is input to a non-linear amplifier (NLA) 102. The non-linear amplifier 102 is a general differential amplifier and amplifies linearly with respect to a small input voltage, but as the input voltage increases, the increase in an output voltage becomes gradual due to saturation characteristics of the amplifier," where the NLA is upstream of and connected to the instant terminals by the circuit).
Regarding Claim 9, the rejection of Claim 8 is incorporated. XXX teaches:
wherein the nonlinear circuit nonlinearly converts a first signal input to the nonlinear circuit to a second signal, wherein the second signal and the first signal satisfy a relational expression of
y
≠
a
x
+
b
, and wherein
y
in the relational expression is the second signal,
x
is the first signal, and
a
and
b
are arbitrary values (Oshima, [0068]: "The non-linear amplifier/buffer 502 first functions as a non-linear amplifier, and an operation thereof is as described in the first embodiment" and [0046]: "when it is necessary to further uniformly increase weight coefficient values of the product-sum calculation, the weight coefficient values of the product-sum calculation can be increased by a gain of the subsequent non-linear amplifier 102. That is, the weight coefficient values of the product-sum calculation of the neuron circuit can be set to a value obtained by multiplying the weight coefficient values of the product-sum calculation in the capacitor array circuit unit 101 by the gain of the non-linear amplifier 102").
Regarding Claim 10, the rejection of Claim 1 is incorporated. Oshima teaches:
wherein the second input terminal is configured to be connectable to a plurality of nodes (Oshima, Fig. 5, depicting analog input INP3 corresponding to the instant second input terminal, per [0036]: "A plurality of analog differential signals are input to a capacitor array circuit unit (CAPARY) 101. The input signals are analog output signals of another neuron circuit .... [F]or example, three differential signals (INP1, INN1), (INP2, INN2), and (INP3, INN3) are input to the capacitor array circuit unit 101" and [0066]: "FIG. 5 shows a configuration of a neuron circuit of a reservoir unit in the reservoir computer of the present embodiment" and [0067]: "Similar to the first embodiment, a plurality of differential signals are input to a capacitor array circuit unit 501").
Regarding Claim 11, the rejection of Claim 1 is incorporated. Oshima teaches:
wherein the first output terminal is configured to be connectable to a plurality of nodes (Oshima, Fig. 5, depicting output terminals AOP or AON, either corresponding to the instant first output terminal, per [0040]: "Differential outputs (AOP, AON) of the buffer 105 are analog outputs of the neuron circuit and are input to the other neuron circuit or the neuron circuit itself" and [0061]: "each of the neuron circuits has an analog output and a digital output, and the analog output (not shown in FIG. 4) is input to another neuron circuit or the neuron circuit itself").
Regarding Claim 14, the rejection of Claim 12 is incorporated. Oshima teaches:
wherein the at least one of the plurality of nodes includes a third input terminal, a second sample and hold circuit (Oshima, Fig. 6, depicting third input terminal INM connected to second sample and hold circuit with capacitors 602, 604, and 606), and a third output terminal (Oshima, Fig. 5, depicting analog output terminal AON),
wherein the third input terminal is configured to be connectable to at least one other node (Oshima, [0083]: "the capacitor array circuit unit 501 has a correspondingly large number of differential input nodes ((IPl, INl) to (IPM, INM))" and [0086]: "by connecting analog output of the other neuron circuit, the analog output of the neuron circuit itself, or analog input from the outside to a necessary number of differential input nodes in accordance with a weight coefficient value of the product-sum calculation, a circuit configuration is the same as that of the capacitor array circuit unit 101"),
wherein a first terminal of the second sample and hold circuit is connected to the third input terminal (Oshima, Fig. 6, depicting the circuit terminal after switch 612 connected to input INM),
wherein a second terminal of the second sample and hold circuit is connected to the third output terminal (Oshima, Fig. 6, depicting the circuit output terminal after switches 614, 616, and 618, which is connected to the third output AON by means of the intermediate components),
wherein the third output terminal is configured to be connectable to at least one other node (Oshima, [0081]: "Differential outputs (AOP, AON) of the buffer 505 are the analog output of the neuron circuit and are input to other neuron circuits or the neuron circuit itself"), and
wherein the second sample and hold circuit holds and converts a propagated signal from the third input terminal (Oshima, [0067]: "Similar to the first embodiment, a plurality of differential signals are input to a capacitor array circuit unit 501, and the capacitor array circuit unit 501 outputs product-sum calculation results for those inputs," where the calculation corresponds to the instant conversion).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (US 2022/0188617 A1, hereinafter "Oshima") in view of Pickett (US 2014/0214738 A1, hereinafter "Pickett").
Regarding Claim 3, the rejection of Claim 2 is incorporated.
Oshima teaches the first sample and hold circuit including a first capacitor.
Oshima does not explicitly teach wherein the first capacitor is a variable capacitor of which a capacitance is variable.
However, Pickett teaches:
wherein the first capacitor is a variable capacitor of which a capacitance is variable (Pickett, [0038]: "FIG. 6 is a flowchart of a method for forming a neuristor-based reservoir computing device .... [T]he neuristors may be designed to have varying performance. For example, the resistance or capacitance values within a neuristor may be intentionally varied").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Oshima regarding the first sample and hold circuit including a first capacitor with those of Pickett regarding wherein the first capacitor is a variable capacitor of which a capacitance is variable.
The motivation to do so would be to facilitate supporting variation in delay and threshold characteristics of the node (Pickett, [0038]: "the ... capacitance values within a neuristor may be intentionally varied to produce the desired variation in delay and threshold characteristics").
Regarding Claim 13, the rejection of Claim 12 is incorporated.
Oshima teaches a reservoir device comprising a plurality of nodes.
Oshima does not explicitly teach wherein at least some of the plurality of nodes are connected in a ring shape.
However, Pickett teaches:
wherein at least some of the plurality of nodes are connected in a ring shape (Pickett, Fig. 1, depicting nodes 108 of reservoir 106 forming cycles in a ring shape, and [0017]: "Inside the reservoir (106), the neuristor nodes are highly interconnected and form a variety of feedback connections that return a certain output to a node or nodes that originally generated the output. This produces feedback loops of the reservoir 'resonate' in response to a given input, set of inputs, or time sequence of inputs").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Oshima regarding a reservoir device comprising a plurality of nodes with those of Pickett regarding wherein at least some of the plurality of nodes are connected in a ring shape.
The motivation to do so would be to facilitate analyzing model inputs in a parallel, fast, and computationally efficient manner (Pickett, [0017]: "Inside the reservoir (106), the neuristor nodes are highly interconnected and form a variety of feedback connections that return a certain output to a node or nodes that originally generated the output. This produces feedback loops of the reservoir 'resonate' in response to a given input, set of inputs, or time sequence of inputs. These resonances and other computational effects of in the reservoir can be used to analyze the inputs in a parallel, extremely fast, and computationally efficient manner").
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Oshima (US 2022/0188617 A1, hereinafter "Oshima") in view of Schie, et al. (US 2023/0376770 A1, hereinafter "Schie").
Regarding Claim 5, the rejection of Claim 2 is incorporated.
Oshima teaches:
... a first clock signal for controlling turning-on/off of the first switch or a second clock signal for controlling turning-on/off of the second switch ... (Oshima, [0055]: "One of the two lanes is used to sample an output voltage of the non-linear amplifier 102 and store the sampled voltage as an electric charge, and the other one is used to supply a voltage based on the stored electric charge to input of the buffer 105. The two lanes change roles by switching the switches, for example, every clock, so that the capacitor memory unit 103 has a function of temporarily storing an input signal").
Oshima does not explicitly teach wherein a first clock signal for controlling turning-on/off of the first switch ... is variable.
However, Schie teaches:
wherein a first clock signal for controlling turning-on/off of the first switch ... is variable (Schie, [0069]: "The above switched charge charge domain circuitry, accepting weighted charge inputs rather than voltage inputs, produces several distinct advantages compared with switched capacitor circuits. Firstly, it is easier to transmit input information as a time pulse which when gating a current source representing weights produces a weighted charge input," where Schie's weighted charge for switching timing correspond to the instant variable clock signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Oshima regarding a first clock signal for controlling turning-on/off of the first switch or a second clock signal for controlling turning-on/off of the second switch with those of Schie regarding wherein a first clock signal for controlling turning-on/off of the first switch is variable.
The motivation to do so would be to facilitate implementation of circuit switching with less noise by means of a simpler implementation (Schie, [0069]: "it is easier to transmit input information as a time pulse which when gating a current source representing weights produces a weighted charge input. ... The noise of the circuit is a fraction of that of a similar switched capacitor circuit since the noise bandwidth is modified by the extremely small conduction time relative to the half period used in a switched capacitor circuit. ... Switched charge based decision circuits and other neural network building blocks can easily be created using similar means and time based mathematics used to easily implement a result").
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Schie, et al. (US 2019/0332459 A1) teach a neural network device implemented by means of multiple switched-charge reservoirs, which perturbs analog neurons to measure neural network error and adjusts weights and biases to converge to a network activation target.
Wu, et al. (US 2023/0244919 A1) teach a reservoir computing device for processing input signal data efficiently, which is implemented by means of reservoir subcircuits using masking and multiplication weights to compute a result value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT N DAY whose telephone number is (703)756-1519. The examiner can normally be reached M-F 9-5.
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/R.N.D./Examiner, Art Unit 2122
/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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