Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/16/2026 has been entered.
Claims 1-7, 9, 11,13, 14, 16, 21, 22, 26 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable Nampoothiri et.al. (U.S Patent Application Publication 2017/0168853; hereinafter Nampoothiri”; Reference cited as prior art in previous office action ) in view of Ahmad et al. (U.S Patent Application Publication2013/0311797); hereinafter “Ahmad ”; Reference cited in previous office action)
Regarding Claim 26 , Nampoothiri discloses , A system comprising
wherein the first circuit is configured to [ “ Interrupt controller ”, Fig.1]:
Receive an early wake value corresponding to a standby mode[0008; “The CPU 12 determines if sleep time prediction is enabled (block 86). Sleep time prediction allows the CPU 12 to determine if the CPU 12 should go to sleep or not. ..”, 0028; “the CPU 12 determines if the calculated completion time is less than a sum of the entry latency and the exit latency for a given low-power mode (LPM) (block 90). Checking to see if the predicted completion time is less than the sum of the latencies effectively insures that the CPU 12 will have time to go all the way into the low-power mode and exit the low-power mode before the end of the transfer. If the answer to block 90 is no, the completion time is greater than the entry and exit latencies, then the CPU 12 determines if early wake-up is enabled (block 92)… then the CPU 12 enables the I/O controller 18 early wake-up generation logic (block 94) and the CPU 12 selects a LPM state (block 96)”, 0029; “the CPU 12 knows a priori its own entry and exit latencies for each low-power mode. The CPU 12 programs the I/O controller 18 with each latency for each low-power mode (block 64). The programming may store values in registers (not shown) within the I/O controller 18. The programming may be performed by software or by directly writing to the registers within the I/O controller 18. Additionally, the CPU 12 may provide information about the current CPU power state (e.g., active or low power).”, 0027; The early wake-up interrupt is passed to the interrupt controller 22, which forwards the early wake-up interrupt to the power management controller 24.”, 0030 ; “ The I/O controller 18 then calculates a first time needed to complete the I/O transfer based on the first transfer rate (block 126). The I/O controller 18 then deducts from the first time an exit latency associated with the logic element to determine an early wake time (block 128).”, 0032; Fig.6; ( i.e determining early wake time based on the corresponding entry and exit latency of the low power mode)]; and
determine a lead time value [ “while the data transfer is nearing completion initiates early wake-up, indicated generally at 142), such that the CPU 12 leaves the low-power mode (generally at 144), taking the exit latency (generally at 146) to become ready to resume active operations..”, 0033; ( i.e. as illustrated in Fig.6, determining the lead time value prior to completion of the data transfer to generate an early wake up )] ;
generate an early wake signal corresponding to the standby mode based on the lead time value [“ “the power management controller 24 begins to wake the CPU 12 by disabling the LPM and performing any other pre-interrupt processing (block 104). Exemplary pre-interrupt processing may depend on I/O data and software, but may include waking up one or more threads, pre-processing metadata, increasing a frequency of the CPU 12 based on processing needs, or the like”, 0031; ( i.e it is apparent that the early wake signal corresponding to the low power mode is generated as power management controller performs pre-processing operations prior to completion of the data transfer)].
A second circuit coupled to the first circuit and configured to [0030; “..the power management controller 24 begins to wake the CPU 12 by disabling the LPM and performing any other pre-interrupt processing (block 104). Exemplary pre-interrupt processing may depend on I/O data and software, but may include waking up one or more threads, pre-processing metadata, increasing a frequency of the CPU 12 based on processing needs, or the like. ..”, 0031; Fig.1] and
subsequent to the first circuit generating the early wake signal, generate the interrupt signal [ 0027; 0031;”.. the I/O controller 18 effectively predicts completion of the data transfer and while the data transfer is nearing completion, initiates early wake-up, indicated generally at 142), such that the CPU 12 leaves the low-power mode (generally at 144), taking the exit latency (generally at 146) to become ready to resume active operations. The end of the exit latency (148) is substantially contemporaneous with the end of the data transfer (150), and the CPU 12 is already in active state 152 so that the next transfer (or other operation) may be started (154).”, 0033] and wherein the system further comprises a memory[“ Memory 16”, Fig.1]
However, Nampoothiri does not expressly disclose, wherein to determine the lead time value based on the early wake value the first circuit is configured to: determine a reference point; and determine the reference point based on full occupancy of the memory.
In the same field of endeavor (e.g. power management by providing advance notice of events when the system is in a low power state and determining an advanced period based on the wake up latency), Ahmad teaches,
wherein to determine the lead time value based on the early wake value [ “.. The advance notice is delivered to the SPMU 240 in order to begin the process of waking up targeted units in system 20. In that manner, when the interrupt is signaled after the timer 270 expires, the units (e.g., core 2Fig.3 , fif.5 a60 and uncore 250) of system 200 are ready to handle the interrupt.”, 0038( i.e determining the advance notice period relative to the scheduled interrupt) ; 0040; “For instance, if the wake up latency is determined to be .DELTA.,(i.e early wake value) then an advance notice is signaled at a time t=T-.DELTA.( (i.e the lead time value). In one embodiment, this is implemented through a second timer, as indicated by line 320, which begins approximately at time t=0 and ends at time t=T-.DELTA.(i.e the lead time value). .. when the scheduled timer interrupt is signaled, the targeted unit(s) has already been awakened and is ready to handle that interrupt at time t=.DELTA..”, 0043; 0047; “At 440, the computer implemented method continues by determining an advance period that is based on the wake up latency of the unit. More particularly, the advance period is used to wake up the unit in time to process the interrupt that is associated with the wake event. In one embodiment, the unit is awakened and active before the interrupt is signaled, such that that unit is ready to handle the interrupt as soon as the interrupt is signaled”, 0048]; the first circuit is configured to: [“ uncore 250 comprises an interrupt controller (not shown) that is used for handling interrupts being delivered to processors in the core configuration 260”, 0035];
determine a reference point [“FIGS. 6A-B combined illustrate a buffer triggered wake advance notice implemented for handling requests for data to fill a buffer when one or more units of a computer system are in low power states. Specifically, FIG. 6A is a flow diagram 600A illustrating a method for power management that implements a buffer triggered wake advance notice technique for waking up core and other units of a computer system.. a buffer triggered wake advance notice technique for waking up core and other units of a computer system”, 0062] ; and
determine the reference point based on full occupancy of the memory[ SPMU 640 is configured to monitor for buffer occupancy of a buffered device 690 (e.g., display, etc.) in order to trigger advance notice 697 of a request for data to fill the buffer 695, wherein the advance notice 697 is used directly to wake up units that are in low power states. A buffer of sufficient size allows for those units to be placed into low power states while the data in the buffer is processed. Advance notice of the request for additional data to fill the buffer is received by the SPMU 640 from the buffered device 690. In that manner, when the request for data is delivered, the memory controller 670 is awake and can immediately handle the request.. “,0065 ; “the buffered device provides notification to the SPMU when the watermark is reached. In another embodiment, the SPMU is configured to monitor the occupancy of the buffer. Once the SPMU is notified, the SPMU is configured to wake up the memory controller. As such, based on the buffer event of reaching the threshold of the buffer, an advance notice is generated allowing the SPMU to start the wake up process of the memory controller. Thereafter, when the request is delivered from the unit to the memory controller for data to fill the buffer, the newly awakened memory controller is ready to process that request.”, 0072; Fig.6A, 6B].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nampoothiri with Ahmad. Ahmad’s teaching of determining an advanced period based on the wake up latency of the respective low power mode to awaken the units , will substantially improve Nampoothiri’s system, to manage power of different units of the computer system and efficiently handle the interrupts instead of waiting for the interrupt to trigger the wake up process by providing an advanced notice with respect to the scheduled interrupt.
Allowable Subject Matter
Claims 1, 11, 21 are allowed.
Response to Arguments
New claim(s) 26 have been considered and rejected with respect to Nampoothiri in view of Ahmad references being used in the current rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimosakoda. , U.S Patent Application Publication 2005/0022044, teaches a clock control circuit and a clock control method which switchingly supply a high-speed clock and a low-speed clock in accordance with the operational state of a system LSI.
Smith et al. , U.S Patent Application Publication 2006/0221759, employing locked loops such as delay-lock loops ("DLL"), and more particularly, to a circuit and method for operating such loops in a manner that minimizes power consumption in memory and other electronic devices.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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