DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 11-14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of copending Application No. 18/784,654 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other. Both claim sets recite a package comprising an integrated device coupled to a substrate via interconnects having a planar cross-section with a concave portion. The only difference is that the examined claims ('420) recite the concave interconnects as ‘pillar interconnects’ on the integrated device, whereas the reference claims ('654) recite them as ‘via interconnects’ on the substrate. Because these interconnects form the mating interface between the two components, it would have been an obvious design choice to a person of ordinary skill in the art to form the concave-shaped interconnect on the substrate rather than the integrated device, as doing so merely shifts the identical interfacial geometry from one mating component to the other to achieve the same predictable electrical and mechanical coupling.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims being examined
Copending application claims
11
1
12
2
13
3
14
4
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Long et al. US 2023/0005870 A1 (hereinafter Long).
Regarding claim 1, Long discloses: An integrated device (Long, chip structure 100 [Para. 0027, Fig. 1A]) comprising:
a die substrate (Long, semiconductor substrate 106 [Fig. 1A]);
and a plurality of pillar interconnects (Long, one or more interconnects 102 [Figs. 1A, 6B])
comprising a first plurality of pillar interconnects (Long, Fig. 6B illustrates various pluralities of interconnects with differing characteristics),
wherein at least one pillar interconnect from the first plurality of pillar interconnects comprises a planar cross sectional shape that includes a concave portion (Long, "one or more interconnects 102 can have…a concave shape" [Para. 0032, Fig. 2]).
Regarding claim 11, Long discloses: A package (Long, "chip structure 100 can be comprised within a chip that further includes one or more semiconductor devices of the example flip chip assembly 112" [Para. 0034, Fig. 1B]. Further, "resonator architecture 800 can be included on one or more chips of flip chip assembly (e.g., the example flip chip assembly 112)" [Para. 0062, Fig. 8]) comprising:
a substrate (Long, piezoelectric layer 802 [Fig. 8]);
and an integrated device coupled to the substrate (Long, "resonator architecture 800 can comprise one or more piezoelectric layers 802 positioned on a semiconductor substrate 106" [Para. 0063]),
wherein the integrated device comprises: a die substrate (Long, semiconductor substrate 106 [Fig. 1A]);
and a plurality of pillar interconnects (Long, one or more interconnects 102 [Figs. 1A, 6B])
comprising a first plurality of pillar interconnects (Long, Fig. 6B illustrates various pluralities of interconnects with differing characteristics),
wherein at least one pillar interconnect from the first plurality of pillar interconnects comprises a planar cross sectional shape that includes a concave portion (Long, "one or more interconnects 102 can have…a concave shape" [Para. 0032, Fig. 2]).
Given that Applicant’s dependent claims in reference to an integrated device and a package disclose the same limitations, and that Long anticipates the limitations set forth in claims 1 and 11, the remaining corresponding claims will be grouped together below for brevity.
Regarding claims 2 and 12, Long further discloses an integrated device/package: wherein the first plurality of pillar interconnects comprises at least one pillar interconnect with a concave shaped wall (Long, "the third stage of manufacturing can further print the one or more interconnects 102 to a desired height" [Para. 0049] wherein "one or more interconnects 102 can have…a concave shape" [Para. 0032, Fig. 2]).
Regarding claims 3 and 13, Long further discloses an integrated device/package: wherein the first plurality of pillar interconnects comprises at least one pillar interconnect with a planar cross sectional shape that includes a cross shape (Long, "the top surface 202 can have…a cross shape" [Para. 0037, Fig. 2]).
Regarding claims 4 and 14, Long further discloses an integrated device/package: wherein the first plurality of pillar interconnects are configured to provide at least one electrical path for power (Long, "one or more interconnects 102 can comprise one or more electrically conductive ink material" [Para. 0031]).
Regarding claims 5 and 15, Long further discloses an integrated device/package: wherein the plurality of pillar interconnects further comprise a second plurality of pillar interconnects (Long, "as shown in FIG. 6B, one or more first interconnects 102 of a given chip can have a different size and/or geometry than one or more second interconnects 102 of the given chip" [Para. 0058]) comprising a planar cross sectional shape that includes a circular shape (Long, "FIG. 6B depicts an example chip structure 100 that includes one or more interconnects 102 having a circular top surface 202" [Para. 0058]).
Regarding claims 6 and 16, Long further discloses an integrated device/package: wherein the first plurality of pillar interconnects and the second plurality of pillar interconnects are arranged in an interleaved manner (Long, Fig. 6B illustrates various pluralities of interconnects arranged in an interleaved manner).
Claims 1, 7-10, 11, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. US 2019/0326240 A1 (hereinafter Chang).
Regarding claim 1, Chang discloses: An integrated device (Chang, work piece 100 [Para. 0019, Fig. 1A) comprising:
a die substrate (Chang, substrate 102 [Para. 0019]);
and a plurality of pillar interconnects (Chang, “array 800 of bump structures” [Para. 0051, Fig. 8])
comprising a first plurality of pillar interconnects (Chang, array 800 in Fig. 8 comprises core region 820, corner region 830, central peripheral region 840, and recess peripheral region 850, each comprising their own plurality of pillar interconnects),
wherein at least one pillar interconnect from the first plurality of pillar interconnects comprises a planar cross sectional shape that includes a concave portion (Chang, “In some embodiments, the curve [of the surface of the recess 510] is concave” [Para. 0042, Figs. 5H-G]).
Regarding claim 11, Chang discloses: A package (Chang, “package structure comprising a Bump-on-Trace (BOT) structure 150” [Para. 0019, Fig. 1A]) comprising:
a substrate (Chang, “Work piece 200 may be a package substrate” [Para. 0021] wherein work piece 200 comprises dielectric layers 214);
and an integrated device coupled to the substrate (Chang, “The package structure 150 includes work piece 100 bonded to work piece 200” [Para. 0019]),
wherein the integrated device comprises: a die substrate (Chang, substrate 102 [Para. 0019]);
and a plurality of pillar interconnects (Chang, “array 800 of bump structures” [Para. 0051, Fig. 8])
comprising a first plurality of pillar interconnects (Chang, array 800 comprises core region 820, corner region 830, central peripheral region 840, and recess peripheral region 850, each comprising their own plurality of pillar interconnects),
wherein at least one pillar interconnect from the first plurality of pillar interconnects comprises a planar cross sectional shape that includes a concave portion (Chang, “In some embodiments, the curve [of the surface of the recess 510] is concave” [Para. 0042, Figs. 5H-G]).
Given that Applicant’s dependent claims in reference to an integrated device and a package disclose the same limitations, and that Chang anticipates the limitations set forth in claims 1 and 11, the remaining corresponding claims will be grouped together below for brevity.
Regarding claims 7 and 17, Chang further discloses an integrated device/package: wherein the first plurality of pillar interconnects comprises a first plurality of core pillar interconnects (Chang, "Array 800 includes a core region 820 having bump structures. Bump structures in core region 820 include non-recessed sides. In some embodiments, at least one bump structure in core region 820 includes a recess" [Para. 0051]).
Regarding claims 8 and 18, Chang further discloses an integrated device/package: wherein the die substrate includes an active region comprising a plurality of logic cells (Chang, "Work piece 100 may be a device die that includes active devices such as transistors" [Para. 0019]).
Regarding claims 9 and 19, Chang further discloses an integrated device/package: further comprising a die interconnection portion coupled to the die substrate (Chang, "Interconnect structure 104, which includes metal lines and vias 106 formed therein and connected to the semiconductor devices, is formed on substrate 102" [Para. 0019]).
Regarding claims 10 and 20, Chang further discloses an integrated device/package:
a plurality of pad interconnects (Chang, metal pad 105 [Para. 0020, Figs. 1A, 2B]);
and a plurality of under bump metallization interconnects (Chang, under-bump metallurgy (UBM) layer 110 [Para. 0020, Fig. 1A])
coupled to (i) the plurality of pad interconnects and (Chang, "The UBM layer 110 is disposed on a metal pad 105" [Para. 0020])
(ii) the plurality of pillar interconnects (Chang, "copper post (or pillar) 112 on UBM layer 110" [Para. 0020]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chidambaram et al. US 2025/0385232 A1 discloses an integrated circuit die with pluralities of pillar interconnects configured in an interleaved manner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GERALD H BISSELL whose telephone number is (571) 272-0834. The examiner can normally be reached Mon - Fri 0800 - 1600.
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/GERALD H. BISSELL/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
