Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pgs. 7-8, filed 4/22/2026, with respect to the rejection(s) of amended claim(s) 1, 11, and 16 under 103 in view of Rooney and Caraccio have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chu.
Applicant includes arguments relative to Chu, because the new limitations in claims 1, 11, and 16 are based on limitations originally included in claims 6 and 15, which in the previous action were rejected in view of Chu. Applicant argues: “Chu appears to be silent to corruption, let alone corrupting data when an ambient temperature is less than a temperature threshold, as generally recited by independent claims 1, 11, and 16.” While Examiner agrees that Chu does not explicitly teach towards performing corruption, Chu does teach maintaining an ambient temperature below a temperature threshold during a memory repair method. (see Chu, para. 1, page. 5 of attached translation: The temperature adjustment range of the cryogenic box is -40°C-40°C, that is, the DDR4 DRAM repair verification method is performed at -40°C-40°C.) In the context of Rooney, who teaches performing data poisoning (corruption) as part of memory repair, the combination clearly teaches performing a memory repair method (including corrupting data) when an ambient temperature is less than a temperature threshold.
Examiner’s Note
Examiner notes that while new claim 21 was rejected, the subject matter therein is very close to overcoming the current combination of references. Examiner recommends amending to include more specific subject matter from para. 59 and 60 from the original specification, that would very likely overcome the current rejections, and may even lead to allowance, subject to further search and consideration. For example:
“wherein the command decoder is operable to stop corrupting data, in response to the ambient temperature being greater than or equal to the temperature threshold, while still performing post package repair on the target portion of memory based on the target memory address.”, in combination with the amendment to claim 1 that specifies corrupting the data and performing PPR when the ambient temperature is less than a target threshold.
This language exemplifies the aspect of the present invention that only the step of corrupting the data is selectively performed based on the temperature, whereas the cited prior art only teaches generally maintaining ambient temperature within a certain range for repair operations (Chu), or stopping all memory operations when a temperature threshold is exceeded (new reference used to reject claim 21: US 20200241989).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 7-14, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rooney (US 2022/0147267), Caraccio (US 2023/0395184), and Chu (CN 117095733).
Regarding claim 1, Rooney teaches:
A device comprising:
a command interface (see fig. 1B: Address Command Input Circuit 105) operable to:
receive a post package repair command and an indication of a target memory address from a host controller; (see fig. 1B: Address Command Input Circuit 105 receives ADDR and CMD) …
and a command decoder coupled to the command interface via a command/address bus (see fig. 1B: Command Decoder 115 and Address Decoder 110 collectively are considered to be a command decoder), wherein the command decoder is operable to:
corrupt data corresponding to a target portion of memory based on the target memory address; (see para. 52: The method 240 begins at block 241 by poisoning data stored to a memory array of the memory device. And see para. 20: the present technology allows a host device of the system, in conjunction with the memory device coupled therewith, to control which bits to invert (to poison) during write or read operations.)
and perform post package repair on the target portion of memory based on the target memory address. (see para. 58: the method 250 begins at block 251 by remapping a first logical address from a first physical address to a second physical address of the memory device. In some embodiments, the remapping is performed in response to a command to enable and/or execute an sPPR operation on the memory device. And see para. 20: the present technology allows a host device of the system, in conjunction with the memory device coupled therewith, to control which bits to invert (to poison) during write or read operations. In some embodiments, the host device may enable and utilize a sPPR function of the memory device to remap a logical address of a memory array between different physical addresses at which known-good and known-bad (e.g., poisoned) data are written.)
However, Rooney does not explicitly disclose:
Disable an input to the command interface based on the post package repair command;
In the analogous art of post package repair, Caraccio teaches:
Disable an input to the command interface based on the post package repair command; (see fig. 3: operation 352, detecting a sPPR request -> operation 354, suspending execution of non-maintenance requests on the target row.) This effectively disables any input that would cause the execution of a non-maintenance request on the target row, for example an additional sPPR request/command.
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney and Caraccio before them, before the effective filing date of the claimed invention, to incorporate disabling an input based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
However, the combination of Rooney and Caraccio does not explicitly teach:
[PPR operations are performed when] an ambient temperature is less than a temperature threshold
In the analogous art of post package repair operations, Chu teaches:
[PPR operations are performed when] an ambient temperature is less than a temperature threshold (para. 1, page. 5 of previously attached translation: The temperature adjustment range of the cryogenic box is -40°C-40°C, that is, the DDR4 DRAM repair verification method is performed at -40°C-40°C.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate only performing PPR operations when the temperature is less than or equal to 40°C into the system for performing post package repair (taught by Rooney and Caraccio), to allow for the benefit of ensuring data will not be lost (Chu, pg. 5, para. 1).
Regarding claim 3, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Caraccio further teaches:
Wherein the command interface is operable to enable the input based on an indication that the command decoder has completed performing the post package repair. (see fig. 3: operation 356, subsequent to completion of the sPPR request, resuming execution of non-maintenance requests on the target row.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate disabling an input based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Regarding claim 4, the combination of Rooney, Caraccio, and Chu teaches the device of claim 3. Caraccio further teaches:
Wherein the command decoder is operable to generate the indication that the command decoder has completed performing the post package repair. (see claim 12: a control circuitry configured to: suspend execution of requests associated with a target address associated with a memory device and a post package repair (PPR) request; … execute the PPR request.) The control circuitry is considered to be a command decoder because it receives and processes commands.
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate disabling an input based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Regarding claim 5, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Rooney further teaches:
The command decoder is operable to:
Corrupt the data corresponding to a plurality of portions of the target portion of memory; (see para 20: the present technology allows a host device of the system, in conjunction with the memory device coupled therewith, to control which bits to invert (to poison).) Each bit can effectively be considered a portion of the target portion of memory.
Perform the post package repair on a subset of the plurality of portions based on the post package repair being performed for a respective portion of the plurality of portions after corrupting the data corresponding to that respective portion. (para. 20: the host device may enable and utilize an sPPR function of the memory device to remap a logical address of a memory array between different physical addresses at which known-good and known-bad (e.g., poisoned) data are written, to permit the poisoning of data without reliance upon test modes or direct data manipulation.)
Regarding claim 7, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Rooney further teaches:
Wherein the command decoder is operable to start performing the post package repair after beginning to corrupt the data. (para. 20: the host device may enable and utilize an sPPR function of the memory device to remap a logical address of a memory array between different physical addresses at which known-good and known-bad (e.g., poisoned) data are written, to permit the poisoning of data without reliance upon test modes or direct data manipulation.)
Regarding claim 8, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Rooney further teaches:
Wherein the command decoder is operable to start performing the post package repair after the data is corrupted. (para. 20: the host device may enable and utilize an sPPR function of the memory device to remap a logical address of a memory array between different physical addresses at which known-good and known-bad (e.g., poisoned) data are written, to permit the poisoning of data without reliance upon test modes or direct data manipulation.)
Regarding claim 9, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Rooney further teaches:
Wherein the target memory address corresponds to
A portion of an emerging memory device memory bank, a random access memory (RAM), a dynamic random access memory (DRAM), (see para. 21: in some embodiments, the memory devices 100 can be DRAM memory devices) Double Data Rate Five Synchronous Dynamic Random-Access Memory (DDR5), Low Power Double Data Rate (LPDDR5) memory, or any combination thereof.
Regarding claim 10, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Caraccio further teaches:
Wherein the command decoder is operable to continue performing normal memory operations after the command interface enables the input. (see fig. 3: operation 356, subsequent to completion of the sPPR request, resuming execution of non-maintenance requests on the target row.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate disabling an input based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Claim 11 corresponds to claim 1, and is rejected accordingly, but for the following added limitations. Rooney teaches:
Securing an indication of a mapping of logical to physical addressing associated with the target memory address based on corrupting data corresponding to a target portion of memory based on the target memory address; (see para. 20: the host device may enable and utilize a sPPR function of the memory device to remap a logical address of a memory array between different physical addresses at which known-good and known-bad (e.g., poisoned) data are written.)
However, Rooney does not explicitly teach:
Enabling the input based on the post package repair and the data being corrupted
Carracio teaches:
Enabling the input based on the post package repair and the data being corrupted (see fig. 3: operation 356, subsequent to completion of the sPPR request, resuming execution of non-maintenance requests on the target row.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate disabling (and reenabling) an input based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Regarding claim 12, the combination of Rooney, Caraccio, and Chu teaches the method of claim 11. Rooney further teaches:
Corrupting the data comprises: corrupting the data corresponding to a target memory bank associated with the target memory address that is to undergo the post package repair at least in part by leaving one or more other memory banks uncorrupted. (para. 9: there are multiple memory arrays in the memory system. And see para. 30: the memory array 150 includes a plurality of banks. And see para. 52: the method 240 begins at block 241 by poisoning data stored to a memory array of a memory device.) If there are multiple memory arrays, each including multiple banks, and only data from one array is corrupted, then there must be at least one other memory bank that is left uncorrupted. Additionally, a memory bank containing target memory address is considered to be a target memory bank.
Claim 13 and 14 correspond to claims 7 and 8 (respectively), and are rejected accordingly.
Regarding claim 15, the combination of Rooney, Caraccio, and Chu teaches the method of claim 11. Rooney further teaches:
[PPR operations include:] corrupt the data corresponding to the target portion of memory based on the target memory address. (see para. 52: The method 240 begins at block 241 by poisoning data stored to a memory array of the memory device. And see para. 20: the present technology allows a host device of the system, in conjunction with the memory device coupled therewith, to control which bits to invert (to poison) during write or read operations.)
However, the combination of Rooney and Caraccio does not explicitly teach:\
Receiving sensed data to indicate the ambient temperature associated with an ambient environment, a device temperature, or both; and
[determining to perform PPR operations] based on determining that the ambient temperature is less than or equal to a threshold.
In the analogous art of post package repair operations, Chu teaches:
Receiving sensed data to indicate the ambient temperature associated with an ambient environment, a device temperature, or both; and [determining to perform PPR operations] based on determining that the ambient temperature is less than or equal to a threshold. (para. 1, page. 5 of attached translation: The temperature adjustment range of the cryogenic box is -40°C-40°C, that is, the DDR4 DRAM repair verification method is performed at -40°C-40°C.) The device is aware that repair operations are performed in the cryogenic box, effectively indicating to the device that the sensed temperature in the box is -40 to 40 degrees, and further is effectively a determination that the ambient temperature inside the box is less than or equal to 40 degrees. The repair operations are performed inside the cryogenic box because it is temperature controlled (less than a threshold temp). This is considered to effectively be a determination to perform the repair operations based on the ambient temperature inside the box being less than or equal to a threshold (40 degrees).
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate only performing PPR operations when the temperature is less than or equal to 40°C into the system for performing post package repair (taught by Rooney and Caraccio), to allow for the benefit of ensuring data will not be lost (Chu, pg. 5, para. 1).
Claim 16 corresponds to claim 1, and is rejected accordingly, but for the following added limitations. Caraccio teaches:
Applying a command mask to a command interface based on the post package repair command. (fig. 3, operation 352: detecting an sPPR request -> operation 354: suspending execution of non-maintenance requests on the target row.) This effectively applies a mask to the command interface by blocking any future non-maintenance commands for the target row.
Removing the command mask based on the post package repair being performed. (fig. 3, operation 356: subsequent to completion of the sPPR request, resuming execution of non-maintenance requests on the target row.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate applying (and removing) a command mask based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Claims 17 and 18 correspond to claim 8 and are rejected accordingly.
Regarding claim 19, the combination of Rooney, Caraccio, and Chu teaches claim 16.
Rooney teaches: performing the data corruption comprises: [receiving sPPR commands]… (para. 52: poisoning data includes issuing or receiving one or more commands to poison the data. The commands can include… one or more commands to execute an sPPR operation.)
Caraccio teaches:
[receiving an sPPR command causes:] writing the target portion of memory to ones or zeros; (fig. 3: operation 352, detecting an sPPR request -> operation 353, writing data stored in target row of a memory array associated with the sPPR request to a buffer) It is well known in the art that writing computer information to a buffer is essentially writing information to ones or zeros.
Generating a new scramble key and wear leveling pointers for an associated memory bank;
Or a combination thereof.
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate applying (and removing) a command mask based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
Regarding claim 20, the combination of Rooney, Caraccio, and Chu teaches claim 16. Rooney further teaches:
Corrupting the data for a first time period; and performing the post package repair for a second time period, wherein the first time period and the second time period at least partially overlap. (para. 52: poisoning data includes issuing or receiving one or more commands to poison the data. The commands can include… one or more commands to execute an sPPR operation.)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Rooney, Caraccio, Chu, and Tekumalla (US Publication No. 2014/0281703).
Regarding claim 2, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Caraccio further teaches:
Wherein the command interface is operable to disable the input and enable the input based on:
…
Ignoring a repair address in response to the post package repair command being issued as a command following a most recent command of alert soft post package repair (ASPPR). (see fig. 3: operation 352, detecting a sPPR request -> operation 354, suspending execution of non-maintenance requests on the target row.) Examiner notes that ASPPR is not a term well known in the art, and upon consulting the specification was unable to find a limiting definition of ASPPR that distinguishes it from sPPR. Therefore, ASPPR is interpreted as a kind of sPPR. Suspending execution of non-maintenance requests on the target row effectively ignores future PPR commands, including the repair addresses associated with them.
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, and Chu before them, before the effective filing date of the claimed invention, to incorporate enabling (and disabling) an input to the command interface based on an sPPR command (taught by Caraccio) into the system for performing post package repair (taught by Rooney and Chu), to allow for benefits such as: remedying the potential hazard of losing data and/or data being unavailable during PPR (Caraccio, para. 42).
However, Rooney, Caraccio, and Chu do not explicitly teach:
[in response to a repair operation being performed] holding an internal chip select (CS) enable signal at a logic low value;
In the analogous art of memory repair, Tekumalla teaches:
[in response to a repair operation being performed] holding an internal chip select (CS) enable signal at a logic low value; (Abstract: during repair [operations], the method disables the chip select for the memory to prevent memory operations until [the repair operations are complete].)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, Chu, and Tekumalla before them, before the effective filing date of the claimed invention, to incorporate holding an internal chip select signal low while repair operations are being performed (taught by Tekumalla) into the system for performing post package repair (taught by Rooney, Caraccio, and Chu), to allow for the benefit of preventing memory operations during repair (Tekumalla, abstract) so that the hazard of losing data during PPR (described by Caraccio, para. 42) may be guaranteed to be avoided.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Rooney, Caraccio, Chu, and Mun (US 2020/0241989).
Regarding claim 21, the combination of Rooney, Caraccio, and Chu teaches the device of claim 1. Rooney further teaches:
[memory operations include] corrupting data (see para. 52: The method 240 begins at block 241 by poisoning data stored to a memory array of the memory device. And see para. 20: the present technology allows a host device of the system, in conjunction with the memory device coupled therewith, to control which bits to invert (to poison) during write or read operations.)
However, the combination of Rooney, Caraccio, and Chu does not explicitly teach:
Stop [performing memory operations] in response to an ambient temperature being greater than or equal to the temperature threshold.
In the analogous art of computer memory management, Mun teaches:
Stop [performing memory operations] in response to an ambient temperature being greater than or equal to the temperature threshold. (para. 101: When the temperature measured by the temperature sensor 172f is greater than or equal to a previously set threshold value, the scheduler 150f stops the memory operation.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Rooney, Caraccio, Chu, and Mun before them, before the effective filing date of the claimed invention, to incorporate stopping memory operations when the ambient temperature is above a threshold into the system for performing post package repair (taught by Rooney, Caraccio, and Chu), to allow for the benefit of preventing memory operations when the temperature is too high (Mun) so that data will not be lost (Chu, pg. 5, para. 1), for example, in the case of a failure of Chu’s low-temperature box.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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