Prosecution Insights
Last updated: October 27, 2026
Application No. 18/784,502

DISPLAY DEVICE

Non-Final OA §103
Filed
Jul 25, 2024
Priority
Jul 26, 2023 — RE 10-2023-0097518
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
629 granted / 688 resolved
+23.4% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
26 currently pending
Career history
732
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
19.1%
-20.9% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 688 resolved cases

Office Action

§103
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2016/0103356 A1) in view of Bok et al. (US 2021/0191552 A1). Regarding independent claim 1: Shin teaches (e.g., Figs. 1-2) a display device, comprising: at least one display panel ([0041]-[0042]: LCP); a plurality of routing lines ([0048]: ALN lines) disposed on an outside surface of at least one side of the at least one transparent display panel (LCP); and a wiring substrate ([0041] and [0048]: ADS) disposed on a rear surface or a top surface of the at least one transparent display panel (LCP), and having a plurality of connection lines ([0056]: TP) connected to the plurality of routing lines (ALN), wherein the plurality of connection lines (TP) extend to the rear surface of the at least one display panel (LCP) to overlap a part of the at least one transparent display panel (LCP). Shin does not expressly teach a transparent display panel and transparent wiring substrate. Bok teaches (Figs. Figs. 1-2 and 25) a display device comprising a transparent display panel (Figs. 1-2 and 25; [0468]) and transparent wiring substrate Fig. 25; [0468]: WL1, Wl2, WL3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the display device comprising a transparent display panel and transparent wiring substrate, as taught by Bok, so that an object or a background arranged or disposed on the lower surface of the display panel may be seen through the upper surface of the display panel (Bok: [0196]) Regarding claim 3. Shin and Bok teach the claim limitation of the display device according to claim 1, on which this claim depends, wherein the at least one transparent display panel includes: a first substrate (Shin: [0009]-[0012] and [0042]: TFS); a second substrate (Shin: [0009]-[0012] and [0042]: CFS) disposed opposite to the first substrate; and an element unit (Shin: [0012] and [0042] and [0044]: LC/TFT) disposed between the first substrate and the second substrate. Regarding claim 4: Shin and Bok teach the claim limitation of the display device according to claim 3, on which this claim depends, Shin as modified by Bok teaches that the element unit includes a thin film transistor (TFT) element layer ([0265]: TFT), a light emitting diode layer (Bok: [0265]: ED), and an encapsulation layer (Bok: [0265]: ENCM), Regarding claim 5: Shin and Bok teach the claim limitation of the display device according to claim 3, on which this claim depends, wherein the second substrate (Shin: TFS) has a size smaller than a size of the first substrate (Shin: CFS) to expose one side of the first substrate, and wherein a plurality of first pads (Shin: [0048]: APD1, APD2) are disposed at the exposed one side of the first substrate (Shin: CFS). Regarding claim 12: Shin and Bok teach the claim limitation of the display device according to claim 1, on which this claim depends, wherein the at least one display panel is sequentially disposed in a horizontal direction or sequentially disposed in a vertical direction (Shin: [0046]-[0047] and [0051]). Allowable Subject Matter Claims 2, 6-11 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “a support layer disposed between the at least one transparent display panel and the transparent wiring substrate to maintain a gap between the at least one transparent display panel and the transparent wiring substrate”. Regarding claim 6: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “a plurality of second pads disposed on a top surface or a rear surface of the transparent wiring substrate to overlap the plurality of first pads”. Claims 7-11 and 19-20 depend from claim 6, and therefore, are allowable for the same reason as claim 6. Regarding claim 13: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “wherein the connection line is disposed on an entire surface of the transparent wiring substrate with a constant pitch”. Regarding claim 14: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “wherein the at least one transparent display panel includes: at least one lower display panel; and at least one upper display panel disposed on the at least one lower display panel”. Regarding claim 15: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “a lower connection line extending to a rear surface of the at least one lower display panel to overlap a part of the at least one lower display panel; and an upper connection line extending to a rear surface of the at least one upper display panel to overlap a part of the at least one upper display panel”. Regarding claim 16: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device comprising: “a first connection line disposed in an up and down direction to overlap a part of a lower side of the at least one transparent display panel; and a second connection line disposed in a left and right direction to overlap a part of at least one of left and right sides of the at least one transparent display panel”. Claims 17-18 depend from claim 16, and therefore, are allowable for the same reason as claim 16. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 25, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+4.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 688 resolved cases by this examiner. Grant probability derived from career allowance rate.

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